Method of making vertical DRAM cross point memory cell

Claim 1

The method for fabricating a vertical DRAM cell which includes a field effect transistor having a Sate electrode and source/drain elements and a capacitor comprising: providing a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate, and a pattern of buried bit lines and a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate; forming a gate dielectric on the surfaces of said holes; forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric; etching said doped polysilicon layer to form said Sate electrode and word lines which are perpendicular to said pattern of buried bit lines; forming said source/drain elements surrounding said Sate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask; wherein said buried bit lines form common and additional said source/drain elements; providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode; forming an opening through said insulating layer surrounding said gate electrode; and forming a capacitor in and over said opening through said insulating layer.

Claim 2

The method for fabricating a vertical DRAM cell which includes a field effect transistor having a Sate electrode and source/drain elements and a capacitor comprising: providing a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate, and a pattern of buried bit lines and a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate; forming a gate dielectric on the surfaces of said holes; forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric; etching said doped polysilicon layer to form said Sate electrode and word lines which are perpendicular to said pattern of buried bit lines; forming said source/drain elements surrounding said Sate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask; wherein said buried bit lines form common and additional said source/drain elements; providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode; forming an opening through said insulating layer surrounding said gate electrode; and forming a capacitor in and over said opening through said insulating layer.

Claim 15

The method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor comprising: providing a base substrate; forming a pattern of buried bit lines in said base substrate, and forming a silicon substrate over said base substrate by epitaxial growth; forming a pattern of field oxide isolation in said silicon substrate wherein there are a pattern of openings to the silicon substrate; forming a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and said buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate; forming a gate dielectric on the surfaces of said holes; forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric: etching said doped polysilicon layer to form said gate electrode and word lines which are perpendicular to said pattern of buried bit lines; forming said source/drain elements surrounding said gate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask; wherein said buried bit lines form common and additional said source/drain elements; providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode; forming an opening through said insulating layer surrounding said gate electrode; and forming a capacitor in and over said opening through said insulating layer.

Claim 16

The method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor comprising: providing a base substrate; forming a pattern of buried bit lines in said base substrate, and forming a silicon substrate over said base substrate by epitaxial growth; forming a pattern of field oxide isolation in said silicon substrate wherein there are a pattern of openings to the silicon substrate; forming a pattern of lines of holes with a hole located within each of said openings to said silicon substrate which lines of holes and said buried bit lines are perpendicular to one another and which said lines cross at the planned locations of said vertical DRAM cell at said pattern of openings to the silicon substrate; forming a gate dielectric on the surfaces of said holes; forming a doped polysilicon layer in and over said holes so that it covers said gate dielectric: etching said doped polysilicon layer to form said gate electrode and word lines which are perpendicular to said pattern of buried bit lines; forming said source/drain elements surrounding said gate electrode in the surface of said substrate by ion implantation using the field oxide and gate electrode and word lines as the mask; wherein said buried bit lines form common and additional said source/drain elements; providing an insulating layer over said pattern of field oxide insulation, said word lines and openings to said source/drain elements surrounding said gate electrode; forming an opening through said insulating layer surrounding said gate electrode; and forming a capacitor in and over said opening through said insulating layer.