Surface mount ic using silicon vias in an area array format or same size as die array

Abstract

Abstract A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material matrix by introduction of a conductive material as known in the art. Such dice may be employed in singulated fashion on a carrier substrate as an alternative to so-called “flip chip” dice, or in vertically-stacked fashion to form a sealed multi-chip module the same size as the die from which it is formed. Certain vias of the various dice in the stack may be vertically aligned or superimposed to provide common access from each die level to a terminal such as a bond pad or C 4 or other connection on the back side of the lowermost die contacting the carrier substrate, while other stacked vias are employed for individual access from each die level to the carrier substrate through the back side of the lowermost die. Vertical or horizontal fuse elements may be employed at some or all die levels to permit different circuit configurations on otherwise identical dice and to isolate devices at certain die levels from selected vias. Vias may be placed at any location within the periphery of a die and are preferably placed in superimposition or immediate lateral proximity to the devices on the various dice to minimize horizontal conductors whenever possible and thus employ more die surface area for device fabrication.

Inventors

• 👤 Warren M. Farnworth

Bibliographic Details