US6383871B1
Expired / Lapsed
US
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Method of forming multiple oxide thicknesses for merged memory and logic applications
Assignee: Micron Technology Inc
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Filing: 1999-08-31
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Granted: 2002-05-07
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Expires: 2019-08-31
Abstract
Abstract Improved methods and structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, improved methods and structures are provided for multiple gate oxide thicknesses on a single chip wherein the chip can include circuitry encompassing a range of technologies including but not limited to the memory and logic technologies. Moreover, these improved methods and structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method for forming a semiconductor device include forming a top layer of SiO 2 on a top surface of a silicon wafer. A trench layer of SiO 2 is also formed on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. Additionally, the formation of the top and trench layers of SiO 2 are such that a thickness of the top layer is different from a thickness of the trench layer.
Inventors
- 👤 Wendell P. Noble
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:21
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383; H10B12/05; H10B12/053; H10B12/09; H10B12/50; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B69/00; H10D; H10D62/00; H10D62/40; H10D62/405; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01346; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/016; H10D84/0165; H10D84/0167; H10D84/0181; H10D84/02; H10D84/03; H10D84/038; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
103 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a top layer of SiO 2 on a top surface of a silicon wafer; and forming a trench layer of SiO 2 on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, wherein a thickness of the top layer is different from a thickness of the trench layer, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800° C.
Claim 2
Independent Claim
103 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a top layer of SiO 2 on a top surface of a silicon wafer; and forming a trench layer of SiO 2 on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, wherein a thickness of the top layer is different from a thickness of the trench layer, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800° C.
Claim 3
Dependent Claim
23 words
The method of claim 1 , wherein forming the top layer of SiO 2 includes forming a gate oxide of a logic device.
Claim 4
Dependent Claim
23 words
The method of claim 1 , wherein forming the trench layer of SiO 2 includes forming a gate oxide of a DRAM cell.
Claim 5
Dependent Claim
44 words
The method of claim 1 , wherein forming the top layer of SiO 2 and forming the trench layer of SiO 2 includes forming the top layer of SiO 2 and forming the trench layer of SiO 2 simultaneously during a linear growth period.
Claim 6
Dependent Claim
39 words
The method of claim 1 , wherein forming the top layer of SiO 2 on the top surface of the silicon wafer includes thermally growing the top layer of SiO 2 on the top surface of the silicon wafer.
Claim 7
Dependent Claim
39 words
The method of claim 1 , wherein forming the trench layer of SiO 2 on the trench wall of the silicon wafer includes thermally growing the trench layer of SiO 2 on the trench wall of the silicon wafer.
Claim 8
Independent Claim
117 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a top surface of a silicon wafer with a top crystalline plane orientation; forming a trench in the silicon wafer, wherein a trench wall has a different crystalline plane orientation than the top crystalline plane orientation; and simultaneously thermally growing a top oxide layer on the top surface and thermally growing a trench oxide layer on the trench wall, during a linear growth period, wherein the top oxide layer has a different thickness than the trench oxide layer, the trench oxide layer having a thickness that is greater than the thickness of the top oxide layer.
Claim 9
Independent Claim
117 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a top surface of a silicon wafer with a top crystalline plane orientation; forming a trench in the silicon wafer, wherein a trench wall has a different crystalline plane orientation than the top crystalline plane orientation; and simultaneously thermally growing a top oxide layer on the top surface and thermally growing a trench oxide layer on the trench wall, during a linear growth period, wherein the top oxide layer has a different thickness than the trench oxide layer, the trench oxide layer having a thickness that is greater than the thickness of the top oxide layer.
Claim 10
Dependent Claim
52 words
The method of claim 7 , wherein thermally growing the top oxide layer on the top surface and thermally growing the trench oxide layer on the trench wall includes thermally growing the trench oxide layer that has a thickness that is approximately 30% thicker than a thickness of the top oxide layer.
Claim 11
Dependent Claim
33 words
The method of claim 7 , wherein thermally growing the top oxide layer includes thermally growing the top oxide layer such that the thickness of the top oxide layer is approximately 70 Angstroms.
Claim 12
Dependent Claim
33 words
The method of claim 7 , wherein thermally growing the trench oxide layer includes thermally growing the trench oxide layer such that the thickness of the trench oxide layer is approximately 100 Angstroms.
Claim 13
Independent Claim
95 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a trench in a silicon wafer, the silicon wafer having a top surface, the trench having a trench wall, such that the trench wall has a (110) crystal plane orientation, wherein the top surface has a (100) crystal plane orientation; and simultaneously thermally oxidizing the top surface to a top thickness and oxidizing the trench wall at a temperature of approximately 800° C. to a trench thickness that is different from the top thickness.
Claim 14
Independent Claim
95 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a trench in a silicon wafer, the silicon wafer having a top surface, the trench having a trench wall, such that the trench wall has a (110) crystal plane orientation, wherein the top surface has a (100) crystal plane orientation; and simultaneously thermally oxidizing the top surface to a top thickness and oxidizing the trench wall at a temperature of approximately 800° C. to a trench thickness that is different from the top thickness.
Claim 15
Dependent Claim
24 words
The method of claim 11 , wherein oxidizing the top surface includes dry oxidizing the top surface at a temperature of approximately 800° C.
Claim 16
Dependent Claim
24 words
The method of claim 11 , wherein oxidizing the trench wall includes dry oxidizing the trench wall at a temperature of approximately 800° C.
Claim 17
Independent Claim
149 words
A method for forming a semiconductor device, comprising: forming a top layer of SiO 2 on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, such that the top layer has a top thickness; and forming a trench layer of SiO 2 on a trench wall of the silicon wafer, wherein the trench wall has a (311) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer, wherein forming the top layer of SiO 2 and forming the trench layer of SiO 2 includes forming the top layer of SiO 2 and forming the trench layer of SiO 2 simultaneously during a linear growth period, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800° C.
Claim 18
Independent Claim
149 words
A method for forming a semiconductor device, comprising: forming a top layer of SiO 2 on a top surface of a silicon wafer, wherein the top surface has a (110) crystal plane orientation, such that the top layer has a top thickness; and forming a trench layer of SiO 2 on a trench wall of the silicon wafer, wherein the trench wall has a (311) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer, wherein forming the top layer of SiO 2 and forming the trench layer of SiO 2 includes forming the top layer of SiO 2 and forming the trench layer of SiO 2 simultaneously during a linear growth period, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800° C.
Claim 19
Independent Claim
104 words
A method of forming a semiconductor device, comprising: forming a top surface of a silicon wafer with a (110) crystalline plane orientation; forming a trench in the silicon wafer, wherein a trench wall has a (511) crystalline plane orientation; and simultaneously thermally growing a top oxide layer on the top surface and thermally growing a trench oxide layer on the trench wall, during a linear growth period, wherein the top oxide layer has a different thickness than the trench oxide layer, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800° C.
Claim 20
Independent Claim
104 words
A method of forming a semiconductor device, comprising: forming a top surface of a silicon wafer with a (110) crystalline plane orientation; forming a trench in the silicon wafer, wherein a trench wall has a (511) crystalline plane orientation; and simultaneously thermally growing a top oxide layer on the top surface and thermally growing a trench oxide layer on the trench wall, during a linear growth period, wherein the top oxide layer has a different thickness than the trench oxide layer, wherein forming the top layer and trench layer include oxidizing the top surface and trench wall at a temperature of approximately 800° C.
Claim 21
Independent Claim
127 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a top layer of SiO 2 on a top surface of a silicon wafer; forming a trench layer of SiO 2 on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, wherein a thickness of the top layer is less than a thickness of the trench layer, wherein forming the top layer includes forming a gate oxide of a top device operating with a voltage of less than about 2.5 volts, and forming the trench layer includes forming a gate oxide of a trench device operating with a voltage of less than about 3.5 volts.
Claim 22
Independent Claim
127 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a top layer of SiO 2 on a top surface of a silicon wafer; forming a trench layer of SiO 2 on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, wherein a thickness of the top layer is less than a thickness of the trench layer, wherein forming the top layer includes forming a gate oxide of a top device operating with a voltage of less than about 2.5 volts, and forming the trench layer includes forming a gate oxide of a trench device operating with a voltage of less than about 3.5 volts.
Claim 23
Dependent Claim
21 words
The method of claim 16 wherein the trench layer is formed having a thickness approximately 30% thicker than the top layer.
Claim 24
Dependent Claim
17 words
The method of claim 16 wherein the thickness of the trench layer formed is approximately 100 Angstroms.
Claim 25
Dependent Claim
17 words
The method of claim 16 wherein the thickness of the top layer formed is approximately 70 Angstroms.
Claim 26
Dependent Claim
23 words
The method of claim 16 wherein forming the trench layer includes forming a trench gate oxide formed to function in a trench device.
Claim 27
Dependent Claim
17 words
The method of claim 20 wherein the trench layer is adapted for use with a DRAM cell.
Claim 28
Dependent Claim
13 words
The method of claim 20 wherein the trench device is an EEPROM device.
Claim 29
Dependent Claim
14 words
The method of claim 22 wherein the trench device includes a flash memory device.
Claim 30
Dependent Claim
18 words
The method of claim 20 wherein the trench device is included as part of a programmable logic array.
Claim 31
Dependent Claim
28 words
The method of claim 16 wherein the semiconductor device further comprises a top device including a top gate separated from the top surface by a top gate oxide.
Claim 32
Dependent Claim
13 words
The method of claim 25 wherein the top device is a logic device.
Claim 33
Dependent Claim
25 words
The method of claim 16 wherein the trench layer is formed on the trench wall through dry oxidization at a temperature of approximately 800° C.
Claim 34
Dependent Claim
25 words
The method of claim 16 wherein the trench layer is formed on the trench wall through wet oxidization at a temperature of approximately 800° C.
Claim 35
Independent Claim
124 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a top layer of SiO 2 on a top surface of a silicon wafer; forming a trench layer of SiO 2 on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, the trench wall has a crystal plane orientation selected from the group consisting of (100), (110), (311), and (511) crystal plane orientations, and the top surface has a crystal plane orientation selected from the group consisting of (100), (110), and (111) crystal plane orientations, and wherein a thickness of the top layer is greater than a thickness of the trench layer.
Claim 36
Independent Claim
124 words
A method for forming a semiconductor device, comprising: forming two different gate oxides for different transistors on a substrate by: forming a top layer of SiO 2 on a top surface of a silicon wafer; forming a trench layer of SiO 2 on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface, the trench wall has a crystal plane orientation selected from the group consisting of (100), (110), (311), and (511) crystal plane orientations, and the top surface has a crystal plane orientation selected from the group consisting of (100), (110), and (111) crystal plane orientations, and wherein a thickness of the top layer is greater than a thickness of the trench layer.
References Cited (Backward Citations)
US3999282A
Cited
US4466178A
Cited
US4651188A
Cited
US4667215A
Cited
US4768076A
Cited
US4857986A
Cited
US5082795A
Cited
US6015737A
Cited
US5196722A
Cited
US5364810A
Cited
US5371383A
Cited
US5915180A
Cited
US5801089A
Cited
US5583368A
Cited
US5883012A
Cited
US5904543A
Cited
US5770878A
Cited
US5998263A
Cited
US5888880A
Cited
US6072209A
Cited
US5907170A
Cited
US6066869A
Cited
US5991225A
Cited
US6097065A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-05-06 | 2005-11-05 | 2006-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-05-06 | 2009-11-05 | 2010-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-05-06 | 2013-11-05 | 2014-05-07 | $7700.00 | Window Closed / Lapsed |