Patent US5289692A successfully refreshed from Google Patents.
Patent US6350993B1 successfully refreshed from Google Patents.
US6350993B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed composite p-channel Si/SiGe heterostructure for field effect devices
Assignee: GlobalFoundries Inc
•
Filing: 1999-03-12
•
Granted: 2002-02-26
•
Expires: 2019-03-12
Abstract
Abstract A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
Inventors
- 👤 Jack Oon Chu
- 👤 Richard Hammond
- 👤 Khalid EzzEldin Ismail
- 👤 Steven John Koester
- 👤 Patricia May Mooney
- 👤 John A. Ott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:30
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/60; H10D30/751; H10D30/791; H10D30/798; H10D62/00; H10D62/10; H10D62/17; H10D62/213
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
169 words
A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si 1−x Ge x formed epitaxially on said substrate where Ge fraction x is in the range from 0.35 to 0.5, a second layer of Si 1−x Ge x formed epitaxially on said first layer, a third layer of undoped Si formed epitaxially on said second layer, a fourth layer of undoped Si 1−x Ge x formed epitaxially on said third layer, a fifth layer of Ge formed epitaxially on said fourth layer whereby said fifth layer is under compressive strain and has a thickness less than its critical thickness with respect to said first layer, a sixth layer of Si 1−w Ge w formed epitaxially on said fifth layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said sixth layer is under compressive strain, and a seventh layer of Si 1−x Ge x formed epitaxially on said sixth layer.
Claim 2
Dependent Claim
169 words
A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si 1−x Ge x formed epitaxially on said substrate where Ge fraction x is in the range from 0.35 to 0.5, a second layer of Si 1−x Ge x formed epitaxially on said first layer, a third layer of undoped Si formed epitaxially on said second layer, a fourth layer of undoped Si 1−x Ge x formed epitaxially on said third layer, a fifth layer of Ge formed epitaxially on said fourth layer whereby said fifth layer is under compressive strain and has a thickness less than its critical thickness with respect to said first layer, a sixth layer of Si 1−w Ge w formed epitaxially on said fifth layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said sixth layer is under compressive strain, and a seventh layer of Si 1−x Ge x formed epitaxially on said sixth layer.
Claim 3
Dependent Claim
57 words
The layered structure of claim 1 further including an over-shoot layer, Si 1−y Ge y , within the strain relief structure of said first layer having a Ge fraction y, where y=x+z and z is in the range from 0.01 to 0.1, and having a thickness less than its critical thickness with respect to said first layer.
Claim 4
Dependent Claim
68 words
The layered structure of claim 1 wherein an active device region is a buried composite channel structure made up of an epitaxial Ge channel of said fifth layer and an epitaxial Si 1−w Ge w channel of said sixth layer having a higher compressive strain to provide a deeper quantum well or a higher barrier for better hole confinement as compared to a single layer channel device alone.
Claim 5
Dependent Claim
44 words
The layered structure of claim 1 wherein said fifth layer is formed at temperatures where 3D growth of Ge films does not occur to generate interface roughness problems and at a temperature range from 275°-350° C. where 2D growth of Ge films does occur.
Claim 6
Dependent Claim
42 words
The layered structure of claim 1 wherein the Ge content w may be graded within said sixth layer starting with a higher Ge content nearer said fifth layer and grading down in Ge content towards the upper surface of said sixth layer.
Claim 7
Dependent Claim
28 words
The layered structure of claim 1 wherein a spacer region comprises said third layer of strained Si and said fourth layer of relaxed Si 1−x Ge x .
Claim 8
Dependent Claim
37 words
The layered structure of claim 1 wherein said third layer is under tensile strain and is commensurate having a thickness below its critical thickness with respect to said first layer at its interface with said second layer.
Claim 9
Dependent Claim
89 words
The layered structure of claim 1 wherein said second layer is a p-doped Si 1−x Ge x layer formed below a channel region of said fifth and sixth layers and separated therefrom by said third layer of Si and said fourth layer of Si 1−x Ge x , said second layer having a thickness in the range from 1 to 20 nm with a preferred thickness from 4 to 5 nm and having an electrically active donor dose in the range from 1 to 3×10 12 cm −2 .
Claim 10
Dependent Claim
64 words
A field-effect transistor structure consisting of the layered structure of claim 1 , further comprising, electrical isolation regions created by the selective removal of at least said seventh through second layer, a Schottky gate electrode formed on said seventh layer, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode.
Claim 11
Dependent Claim
70 words
A field-effect transistor structure consisting of the layered structure of claim 1 , further comprising, electrical isolation regions created by the selective removal of at least said seventh through second layer, a gate dielectric formed on said seventh layer, a gate electrode on said gate dielectric, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode.
Claim 12
Dependent Claim
154 words
A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si 1−x Ge x formed epitaxially on said substrate where Ge fraction x is in the range from 0.35 to 0.5, a second layer of Si 1−x Ge x formed epitaxially on said first layer, a third layer of undoped Si formed epitaxially on said second layer, a fourth layer of Ge formed epitaxially on said third layer whereby said fourth layer is under compressive strain and having a thickness less than its critical thickness with respect to said first layer, a fifth layer of Si 1w Ge w formed epitaxially on said fourth layer wherein the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said fifth layer is under compressive strain, and a sixth layer of Si 1−x Ge x formed epitaxially on said fifth layer.
Claim 13
Dependent Claim
154 words
A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si 1−x Ge x formed epitaxially on said substrate where Ge fraction x is in the range from 0.35 to 0.5, a second layer of Si 1−x Ge x formed epitaxially on said first layer, a third layer of undoped Si formed epitaxially on said second layer, a fourth layer of Ge formed epitaxially on said third layer whereby said fourth layer is under compressive strain and having a thickness less than its critical thickness with respect to said first layer, a fifth layer of Si 1w Ge w formed epitaxially on said fourth layer wherein the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said fifth layer is under compressive strain, and a sixth layer of Si 1−x Ge x formed epitaxially on said fifth layer.
Claim 14
Dependent Claim
57 words
The layered structure of claim 11 further including an over-shoot layer, Si 1−y Ge y , within the strain relief structure of said first layer having a Ge fraction y, where y=+z and z is in the range from 0.01 to 0.1, and having a thickness less than its critical thickness with respect to said first layer.
Claim 15
Dependent Claim
68 words
The layered structure of claim 11 wherein an active device region is a buried composite channel structure made up of an epitaxial Ge channel of said fourth layer and an epitaxial Si 1−w Ge w channel of said fifth layer having a higher compressive strain to provide a deeper quantum well or a higher barrier for better hole confinement as compared to a single layer channel device alone.
Claim 16
Dependent Claim
44 words
The layered structure of claim 11 wherein said fourth layer is formed at temperatures where 3D growth of Ge films does not occur to generate interface roughness problems and at a temperature range from 275-350° C. where 2D growth of Ge films does occur.
Claim 17
Dependent Claim
42 words
The layered structure of claim 11 wherein the Ge content w may be graded within said fifth layer starting with a higher Ge content nearer said fourth layer and grading down in Ge content towards the upper surface of said fifth layer.
Claim 18
Dependent Claim
27 words
The layered structure of claim 11 wherein a spacer region is a single layer structure comprised of said third layer wherein said third layer is strained Si.
Claim 19
Dependent Claim
37 words
The layered structure of claim 11 wherein said third layer is under tensile strain and is commensurate having a thickness below its critical thickness with respect to said first layer at its interface with said second layer.
Claim 20
Dependent Claim
58 words
The layered structure of claim 11 wherein said third layer Si may be substituted with a relaxed Si 1−x Ge x layer with an adjustable thickness to allow the spacer thickness to be varied accordingly whereby the supply dose may be optimized for device applications as a function of temperature in the range from 0.4 to 425 K.
Claim 21
Dependent Claim
36 words
The layered structure of claim 18 wherein the supply layer of said second layer is formed and separated below the channel region of said fourth and fifth layers by said relaxed Si 1−x Ge x layer.
Claim 22
Dependent Claim
38 words
The layered structure of claim 11 wherein said second layer is a p-doped Si 1−x Ge x layer formed below a channel region of said fourth and fifth layers and separated therefrom by said third layer of Si.
Claim 23
Dependent Claim
64 words
A field-effect transistor structure consisting of the layered structure of claim 11 , further comprising, electrical isolation regions created by the selective removal of at least said sixth through second layer, a Schottky gate electrode formed on said sixth layer, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode.
Claim 24
Dependent Claim
70 words
A field-effect transistor structure consisting of the layered structure of claim 9 , further comprising, electrical isolation regions created by the selective removal of at least said sixth through second layer, a gate dielectric formed on said sixth layer, a gate electrode on said gate dielectric, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode.
Claim 25
Dependent Claim
155 words
A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si 1−x Ge x formed epitaxially on said substrate where Ge fraction x is the range from 0.35 to 0.5, a second layer of Ge formed epitaxially on said first layer whereby said second layer is under compressive strain and having a thickness less than its critical thickness with respect to said first layer, a third layer of Si 1−w Ge w formed epitaxially on said second layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said third layer is under compressive strain, a fourth layer of undoped Si 1−x Ge x formed epitaxially on said third layer, a fifth layer of undoped Si formed epitaxially on said fourth layer, and a sixth layer of p-doped Si 1−x Ge x formed epitaxially on said fifth layer.
Claim 26
Dependent Claim
155 words
A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si 1−x Ge x formed epitaxially on said substrate where Ge fraction x is the range from 0.35 to 0.5, a second layer of Ge formed epitaxially on said first layer whereby said second layer is under compressive strain and having a thickness less than its critical thickness with respect to said first layer, a third layer of Si 1−w Ge w formed epitaxially on said second layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said third layer is under compressive strain, a fourth layer of undoped Si 1−x Ge x formed epitaxially on said third layer, a fifth layer of undoped Si formed epitaxially on said fourth layer, and a sixth layer of p-doped Si 1−x Ge x formed epitaxially on said fifth layer.
Claim 27
Dependent Claim
56 words
The layered structure of claim 23 further including an over-shoot layer, Si 1−y Ge y within the strain relief structure of said first layer having a Ge fraction y, where y=x+z and z is in the range from 0.01 to 0.1, and having a thickness less than its critical thickness with respect to said first layer.
Claim 28
Dependent Claim
68 words
The layered structure of claim 23 wherein an active device region is a buried composite channel structure made up of an epitaxial Ge channel of said second layer and an epitaxial Si 1−w Ge w channel of said third layer having a higher compressive strain to provide a deeper quantum well or a higher barrier for better hole confinement as compared to a single layer channel device alone.
Claim 29
Dependent Claim
44 words
The layered structure of claim 23 wherein said second layer is formed at temperatures where 3D growth of Ge films does not occur to generate interface roughness problems and at a temperature range from 275°-350° C. where 2D growth of Ge films does occur.
Claim 30
Dependent Claim
41 words
The layered structure of claim 23 wherein the Ge content w may be graded within said third layer starting with a higher content nearer said second layer and grading down in Ge content towards the upper surface of said third layer.
Claim 31
Dependent Claim
33 words
The layered structure of claim 23 wherein a spacer region is a composite layer structure comprising said fifth layer of strained Si and said fourth layer of relaxed Si 1−x Ge x .
Claim 32
Dependent Claim
37 words
The layered structure of claim 23 wherein said fifth layer is under tensile strain and is commensurate having a thickness below its critical thickness with respect to said first layer at its interface with said second layer.
Claim 33
Dependent Claim
57 words
The layered structure of claim 23 wherein the supply layer is a p-doped Si 1−x Ge x layer of said sixth layer formed above a channel region of said second and third layers and is separated by a composite spacer structure of said fifth layer of Si and said fourth layer of Si 1−x Ge x .
Claim 34
Dependent Claim
70 words
A field-effect transistor structure consisting of the layered structure of claim 23 , further comprising, electrical isolation regions created by the selective removal of at least said sixth through second layer, a gate dielectric formed on said sixth layer, a gate electrode on said gate dielectric, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode.
Claim 35
Dependent Claim
143 words
A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si 1−x Ge x formed epitaxially on said substrate where Ge fraction x is the range from 0.35 to 0.5, a second layer of Ge formed epitaxially on said first layer whereby said second layer is under compressive strain and has a thickness less than its critical thickness with respect to said first layer, a third layer of Si 1−w Ge w formed epitaxially on said second layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said third layer is under compressive strain, a fourth layer of undoped Si 1−x Ge x formed epitaxially on said third layer, and a fifth layer of p-doped Si 1−x Ge x formed epitaxially on said fourth layer.
Claim 36
Dependent Claim
143 words
A layered structure for forming p-channel field effect transistors comprising: a single crystalline substrate, a first layer of relaxed Si 1−x Ge x formed epitaxially on said substrate where Ge fraction x is the range from 0.35 to 0.5, a second layer of Ge formed epitaxially on said first layer whereby said second layer is under compressive strain and has a thickness less than its critical thickness with respect to said first layer, a third layer of Si 1−w Ge w formed epitaxially on said second layer where the Ge fraction w is in the range from 0.5 to <1.0 and where w−x >0.2 whereby said third layer is under compressive strain, a fourth layer of undoped Si 1−x Ge x formed epitaxially on said third layer, and a fifth layer of p-doped Si 1−x Ge x formed epitaxially on said fourth layer.
Claim 37
Dependent Claim
57 words
The layered structure of claim 32 further including an over-shoot layer, Si 1−y Ge y , within the strain relief structure of said first layer having a Ge fraction y, where y=x+z and z is in the range from 0.01 to 0.1, and having a thickness less than its critical thickness with respect to said first layer.
Claim 38
Dependent Claim
69 words
The layered structure of claim 32 wherein an active device region is a buried composite channel structure made up of an epitaxial Ge channel of said second layer and an epitaxial Si 1−w Ge w . channel of said third layer having a higher compressive strain to provide a deeper quantum well or a higher barrier for better hole confinement as compared to a single layer channel device alone.
Claim 39
Dependent Claim
44 words
The layered structure of claim 32 wherein said second layer is formed at temperatures where 3D growth of Ge films does not occur to generate interface roughness problems and at a temperature range from 275°-350° C. where 2D growth of Ge films does occur.
Claim 40
Dependent Claim
41 words
The layered structure of claim 32 wherein the Ge content w may be graded within said third layer starting with a higher content nearer said second layer and grading down in Ge content towards the upper surface of said third layer.
Claim 41
Dependent Claim
28 words
The layered structure of claim 32 wherein a spacer region is a single layer structure comprised of a relaxed Si 1−x Ge x layer of said fourth layer.
Claim 42
Dependent Claim
37 words
The layered structure of claim 32 wherein said fourth layer of Si 1−x Ge x may be substituted with a thin strained commensurate Si layer whereby a thin spacer thickness may be provided for a MODFET device.
Claim 43
Dependent Claim
39 words
The layered structure of claim 38 wherein said fifth layer is a p-doped Si 1−x Ge x layer formed above a channel region of said second and third layers and separated therefrom by a thin strained commensurate Si layer.
Claim 44
Dependent Claim
42 words
The layered structure of claim 32 wherein said fifth layer is a p-doped Si 1−x Ge x layer formed above a channel region of said second and third layers and separated therefrom by said fourth layer of Si 1−x Ge x .
Claim 45
Dependent Claim
70 words
A field-effect transistor structure consisting of the layered structure of claim 32 , further comprising, electrical isolation regions created by the selective removal of at least said fifth through second layer, a gate dielectric formed on said fifth layer, a gate electrode on said gate dielectric, a source electrode located on one side of said gate electrode, and a drain electrode located on the other side of said gate electrode.
References Cited (Backward Citations)
US5350940A
Cited
US5298452A
Cited
US5036374A
Cited
US4994866A
Cited
US5241197A
Cited
US5019882A
Cited
US5272365A
Cited
US5223724A
Cited
US5216271A
Cited
US5821577A
Cited
US5221413A
Cited
US5442205A
Cited
US5659187A
Cited
US5259918A
Cited
US5285088A
Cited
US5726487A
Cited
US5461250A
Cited
US5451800A
Cited
US5523592A
Cited
US5357119A
Cited
US5436474A
Cited
US5534713A
Cited
US5698869A
Cited
US5561302A
Cited
US5665981A
Cited
US5686744A
Cited
US6059895A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-25 | 2005-08-27 | 2006-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-25 | 2009-08-27 | 2010-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-25 | 2013-08-27 | 2014-02-26 | $7700.00 | Window Closed / Lapsed |