US6323680B1 — Programmable logic device configured to accommoda…

Claim 1

Independent Claim 153 words

A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions; wherein: each region in at least a subset of said plurality of regions of programmable logic has additional logic dedicated to the performance of functions forming at least part of a multiplication operation; and said additional logic comprises a first logic unit for performing at least portions of both (i) two partial products of two multiplicands and (ii) summing said two partial products.

Claim 2

Dependent Claim 153 words

A programmable logic device comprising: a plurality of regions of programmable logic, each having a plurality of input terminals and at least one output terminal, and each being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal; and an interconnection network which is programmable to selectively connect the output terminal of substantially any of the regions to at least one of the input terminals of substantially any of the regions; wherein: each region in at least a subset of said plurality of regions of programmable logic has additional logic dedicated to the performance of functions forming at least part of a multiplication operation; and said additional logic comprises a first logic unit for performing at least portions of both (i) two partial products of two multiplicands and (ii) summing said two partial products.

Claim 3

Dependent Claim 62 words

The programmable logic device of claim 1 wherein said first logic unit comprises a multiplexer having as inputs (a) at least one bit of one of said two multiplicands and (b) at least one bit of the product of 2 and said one of said two multiplicands, and having as control signals at least one digit of another of said two multiplicands.

Claim 4

Dependent Claim 26 words

The programmable logic device of claim 2 wherein said multiplexer further has as an input (c) a sum of said input (a) and said input (b).

Claim 5

Dependent Claim 25 words

The programmable logic device of claim 3 wherein said sum of said input (a) and said input (b) is formed in said programmable logic region.

Claim 6

Dependent Claim 20 words

The programmable logic device of claim 3 wherein said multiplexer further has as an input (d) a single programmable bit.

Claim 7

Dependent Claim 17 words

The programmable logic device of claim 2 wherein said multiplexer has as control signals two said digits.

Claim 8

Dependent Claim 27 words

The programmable logic device of claim 1 wherein at least one input of said additional logic is programmably invertible for inversion of output of said additional logic.

Claim 9

Dependent Claim 63 words

The programmable logic device of claim 1 wherein: said region has a plurality of inputs for applying said input signals on which said logic functions are performed and for applying signals common to a plurality of said regions; and when said additional logic is in use, input signals to said additional logic are applied to one or more of said plurality of inputs.

Claim 10

Dependent Claim 38 words

The programmable logic device of claim 8 wherein at least one of said input signals to said additional logic is applied to at least one of said inputs for applying signals common to a plurality of said regions.

Claim 11

Dependent Claim 102 words

The programmable logic device of claim 1 wherein said additional logic further comprises: a second said logic unit, said first logic unit performing said sum of partial products assuming a first value of a carry from another said region, and said second logic unit performing said sum of partial products assuming a second value of said carry; a carry input for said carry from said another said region; and a carry select unit for selecting said sum of partial products from one of said first and second logic units based on whether said carry has said first value or said second value.

Claim 12

Dependent Claim 21 words

The programmable logic device of claim 1 wherein said additional logic has a dedicated sum output separate from said output terminal.

Claim 13

Dependent Claim 93 words

The programmable logic device of claim 1 wherein: said regions are arranged in rows and columns; said additional logic produces a carry value, and includes a dedicated carry input for receiving a carry value from additional logic of another said region and a dedicated carry output for sending a carry value to additional logic of another said region; and said interconnect network includes dedicated carry connections connecting said dedicated carry output of one of said regions to said dedicated carry input of another of said regions directly below said one of said regions.

Claim 14

Dependent Claim 46 words

The programmable logic device of claim 12 wherein: said regions are arranged in groups on said programmable logic device; and each said region has one of said dedicated carry connections, regardless of whether said one of said dedicated carry connections extends between groups of said regions.

Claim 15

Dependent Claim 45 words

The programmable logic device of claim 1 wherein: said multiplication is performed by summing sums of partial products from a particular number of said regions; and said interconnect network includes dedicated connections among a selected number of said regions for performing said summing of sums.

Claim 16

Dependent Claim 136 words

The programmable logic device of claim 14 wherein: said regions are arranged in columns; among a group of said columns of said regions programmed to perform multiplication, said selected number of said regions are in even-numbered ones of said columns; a left input to each of said selected number of regions in a column numbered 2N is provided with one of said dedicated connections to an output of a corresponding logic region located 0.5Q(2N) columns left of said column numbered 2N; and a right input to each of said selected number of regions in said column numbered 2N is provided with one of said dedicated connections to an output of a corresponding logic region located 0.5Q(2N) columns right of said column numbered 2N; where Q(2N) is a largest integral power of 2 that evenly divides 2N.

Claim 17

Dependent Claim 47 words

The programmable logic device of claim 1 wherein: said multiplication is performed by summing sums of partial products from a particular number of said regions; and said programmable logic device further comprises a plurality of dedicated adders for adding sums of partial products produced by said regions.

Claim 18

Dependent Claim 130 words

The programmable logic device of claim 16 wherein: said regions and said adders are arranged in alternating columns; among a group of said columns of said regions programmed to perform multiplication, said adders are in even-numbered ones of said columns; a left input to each of said adders in a column numbered 2N is provided with one of said dedicated connections to an output of a corresponding logic region located 0.5Q(2N) columns left of said column numbered 2N; and a right input to each of said adders in said column numbered 2N is provided with one of said dedicated connections to an output of a corresponding logic region located 0.5Q(2N) columns right of said column numbered 2N; where Q(2N) is a largest integral power of 2 that evenly divides 2N.

Claim 19

Dependent Claim 32 words

A digital processing system comprising: processing circuitry; a memory coupled to said processing circuitry; and a programmable logic device as defined in claim 2 coupled to the processing circuitry and the memory.

Claim 20

Dependent Claim 18 words

A printed circuit board on which is mounted a programmable logic device as defined in claim 1 .

Claim 21

Dependent Claim 25 words

The printed circuit board defined in claim 19 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

Claim 22

Dependent Claim 24 words

The printed circuit board defined in claim 20 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

Claim 23

Dependent Claim 108 words

A programmable logic region for use in a programmable logic device, said programmable logic region comprising a plurality of input terminals and at least one output terminal, and being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal, said region further having: additional logic dedicated to the performance of functions forming at least part of a multiplication operation; wherein: said additional logic comprises a first logic unit for performing at least portions of both (i) two partial products of two multiplicands and (ii) summing said two partial products.

Claim 24

Dependent Claim 108 words

A programmable logic region for use in a programmable logic device, said programmable logic region comprising a plurality of input terminals and at least one output terminal, and being programmable to selectively perform any of a plurality of logic functions on input signals applied to the input terminals to produce an output signal applied to the output terminal, said region further having: additional logic dedicated to the performance of functions forming at least part of a multiplication operation; wherein: said additional logic comprises a first logic unit for performing at least portions of both (i) two partial products of two multiplicands and (ii) summing said two partial products.

Claim 25

Dependent Claim 61 words

The programmable logic region of claim 22 wherein said first logic unit comprises a multiplexer having as inputs (a) at least one bit of one said two multiplicands and (b) at least one bit of the product of 2 and said one of said two multiplicands, and having as control signals at least one digit of another of said two multiplicands.

Claim 26

Dependent Claim 26 words

The programmable logic region of claim 23 wherein said multiplexer further has as an input (c) a sum of said input (a) and said input (b).

Claim 27

Dependent Claim 25 words

The programmable logic region of claim 24 wherein said sum of said input (a) and said input (b) is formed in said programmable logic region.

Claim 28

Dependent Claim 20 words

The programmable logic region of claim 24 wherein said multiplexer further has as an input (d) a single programmable bit.

Claim 29

Dependent Claim 17 words

The programmable logic region of claim 23 wherein said multiplexer has as control signals two said digits.

Claim 30

Dependent Claim 27 words

The programmable logic region of claim 22 wherein at least one input of said additional logic is programmably invertible for inversion of output of said additional logic.

Claim 31

Dependent Claim 63 words

The programmable logic region of claim 22 wherein: said region has a plurality of inputs for applying said input signals on which said logic functions are performed and for applying signals common to a plurality of said regions; and when said additional logic is in use, input signals to said additional logic are applied to one or more of said plurality of inputs.

Claim 32

Dependent Claim 38 words

The programmable logic region of claim 29 wherein at least one of said input signals to said additional logic is applied to at least one of said inputs for applying signals common to a plurality of said regions.

Claim 33

Dependent Claim 102 words

The programmable logic region of claim 22 wherein said additional logic further comprises: a second said logic unit, said first logic unit performing said sum of partial products assuming a first value of a carry from another said region, and said second logic unit performing said sum of partial products assuming a second value of said carry; a carry input for said carry from said another said region; and a carry select unit for selecting said sum of partial products from one of said first and second logic units based on whether said carry has said first value or said second value.

Claim 34

Dependent Claim 21 words

The programmable logic region of claim 22 wherein said additional logic has a dedicated sum output separate from said output terminal.

Claim 35

Dependent Claim 52 words

The programmable logic region of claim 22 wherein: said additional logic produces a carry value; and said region includes a dedicated carry input for receiving a carry value from additional logic of another said region and a dedicated carry output for sending a carry value to additional logic of another said region.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2004-11-26	2005-05-28	2005-11-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2008-11-26	2009-05-28	2009-11-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2012-11-26	2013-05-28	2013-11-27	$7700.00	Window Closed / Lapsed

Programmable logic device configured to accommodate multiplication

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