Programmable logic array integrated circuits with carry and/or cascade rings

Claim 1

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic, each of which has an input for a carry/cascade signal and an output for a carry/cascade signal, said logic regions being disposed on said integrated circuit in an ordered series in which successive logic regions in said series are physically adjacent to one another; and a plurality of carry/cascade signal paths, each of which is usable substantially only for conveying a carry/cascade signal, each of said carry/cascade signal paths extending from a respective one of said outputs to a respective one of said inputs, the input and output associated with each of said carry/cascade signal paths being the input and output of different ones of said logic regions so that said carry/cascade signal paths collectively interconnect said logic regions in a closed loop, said series being further divided into two interdigitated subseries which are mutually exclusive and collectively exhaustive, wherein carry/cascade signal paths interconnect successive logic regions in a first of said subseries in series order, wherein carry/cascade signal paths interconnect successive logic regions in a second of said subseries in reverse series order, and wherein at each end of said subseries a carry/cascade signal path interconnects said subseries by interconnecting adjacent logic regions at said end of said subseries.