US4815022A
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Programmable logic array for carrying out logic operations of binary input signals
Assignee: Siemens AG
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Filing: 1987-05-20
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Granted: 1989-03-21
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Expires: 2007-05-20
Abstract
Abstract A programmable circuit for carrying out logic operations on binary input signals. The programmable circuit contains a matrix of first lines crossed with second lines thereby defining intersections at which logic units corresponding to a function table are connected. Two of the first lines are combined to form a line pair. The matrix is programmed in that a logic unit is connected between one of the lines of the line pair and a second line for the binary value of "1" and a logic unit is connected between the other of the lines of the line pair and the second line for programming a binary value of "0". Utilizing control signals, the logic units can be activated either in one direction or the other. Therefore, it is thus possible to set a line pair either as an input or as an output of the programmable circuit. When a line pair acts as an input, the binary signals coupled into the second lines by the logic units are subjected to an AND operation on the second lines. When a line pair is operated as an output, then the binary signals coupled from the second lines onto the first lines of the line pair by the logic units are subjected to a NOR operation.
Inventors
- 👤 Winfried Glaeser
- 👤 Dieter Schuett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:26
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5057; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
206 words
A programmable circuit for performing logic operations on binary input signals having a matrix with crossed first and second lines, each of said first and second lines connected through as respective resistor to an operating voltage source, and also having logic units connected at intersections between the first lines and the second lines, comprising: at least one line pair formed from two first lines; a plurality of bidirectional operable logic units, a respective logic unit of said plurality of logic units being connected between one of said first lines of said line pair and each of said second lines and a respective logic unit of said plurality of logic units being connected between the other of said first lines of said line pair and each of said second lines; bidirectional operable driver circuit connected to an end of said one of said first lines of said line pair which is opposed to an end of said one of said first lines which is connected to the voltage source; and driver stage connected to an end of the other of said first lines of said line pair which is opposed to an end of said other of said first lines which is connected to the voltage source.
Claim 2
Dependent Claim
206 words
A programmable circuit for performing logic operations on binary input signals having a matrix with crossed first and second lines, each of said first and second lines connected through as respective resistor to an operating voltage source, and also having logic units connected at intersections between the first lines and the second lines, comprising: at least one line pair formed from two first lines; a plurality of bidirectional operable logic units, a respective logic unit of said plurality of logic units being connected between one of said first lines of said line pair and each of said second lines and a respective logic unit of said plurality of logic units being connected between the other of said first lines of said line pair and each of said second lines; bidirectional operable driver circuit connected to an end of said one of said first lines of said line pair which is opposed to an end of said one of said first lines which is connected to the voltage source; and driver stage connected to an end of the other of said first lines of said line pair which is opposed to an end of said other of said first lines which is connected to the voltage source.
Claim 3
Dependent Claim
22 words
A programmable circuit according to claim 1, wherein said logic unit comprises two switch elements connected in anti-parallel fashion and separately disconnectable.
Claim 4
Dependent Claim
30 words
A programmable circuit according to claim 2, wherein one of said switch elements is a non-inverting switch element and the other of said switch elements is an inverting switch element.
Claim 5
Dependent Claim
71 words
A programmable circuit according to claim 3, wherein each of said switch elements have an output circuit with an open-collector output transistor circuit which forms a non-inverting switch element when a zero binary value is received by the switch element and which forms an inverting switch element when a one binary value is received by the switch element thereby applying a fixed potential to a line connected to said output circuit.
Claim 6
Dependent Claim
22 words
A programmable circuit according to claim 3, wherein said driver circuit comprises two driver sections connected in anti-parallel fashion and separately disconnectable.
Claim 7
Dependent Claim
30 words
A programmable circuit according to claim 3, wherein one of said driver sections is a non-inverting driver section and the other of said driver section is an inverting driver section.
Claim 8
Dependent Claim
31 words
A programmable circuit according to claim 6, wherein for operation of said line pair as an input, said non-inverting driver sections and said non-inverting switches of said logic units are activated.
Claim 9
Dependent Claim
31 words
A programmable circuit according to claim 6, wherein for operation of said line pair as an output, said inverting driver sections and said inverting switches of said logic units are activated.
Claim 10
Dependent Claim
26 words
A programmable circuit according to claim 6, wherein switching of said switching elements and of said driver sections is initiated by at least one control signal.
Claim 11
Dependent Claim
30 words
A programmable circuit according to claim 1, wherein said driver stage is an inverter and wherein for operation of said line pair as an input, said driver stage is activated.
Claim 12
Dependent Claim
49 words
A programmable circuit according to claim 1, wherein said logic unit is connected at a selected intersection between said second line and a selected one of said first lines of said line pair when a column in a function table representing the logic operation prescribes a predetermined binary value.
Claim 13
Dependent Claim
40 words
A programmable circuit according to claim 11, wherein, for operation of said first lines as inputs, said logic units are activated and provide binary signals to said second lines from said first lines to carry out a logical AND operation.
Claim 14
Dependent Claim
40 words
A programmable circuit according to claim 12, where, for operation of said first lines as outputs, said logic units are activated and provide binary signals from said second lines to said first lines to carry out a logical NOR operation.
Claim 15
Dependent Claim
38 words
A programmable circuit according to claim 1, wherein said second lines are connected to an OR circuit which produces an output signal representative of an input bit pattern applied to the matrix being contained in a function table.
Claim 16
Dependent Claim
66 words
A programmable circuit according to claim 1, wherein said circuit further comprises a testing network which, when said line pair is operated as an output, compares a first signal generated on said other of said first lines of said line pair to a second signal generated from an output of said bidirectional operable driver circuit of said one of said first lines of said line pairs.
Claim 17
Dependent Claim
31 words
A programmable circuit according to claim 15, wherein said testing network generates an error signal when said first signal is a binary "1" and said second signal is a binary "0".
Claim 18
Dependent Claim
23 words
A programmable circuit according to claim 16, wherein said testing network has a separate AND circuit connected to each of said line pairs.
Claim 19
Dependent Claim
204 words
A programmable circuit for performing logic operations comprising: matrix having a plurality of first lines crossing a plurality of second lines to define a plurality of intersections, said first lines grouped by twos to form a plurality of line pairs, each having an A first line and a B first line; means for bidirectionally connecting each of said first lines to each of said second lines including in series a means for switching and a means for disconnecting; a plurality of first means for bidirectionally driving a signal, respectively connected to a first end of said A first line of each of said line pairs; a plurality of second means for driving a signal, respectively connected to a first end of said B first line of each of said line pairs; and means for supplying a voltage to second ends of said first and second lines; wherein for performing a selected logic operation predetermined ones of said means for bidirectional connecting are deactivated by their respective means for disconnecting such that each of said second lines is connected by predetermined others of said means for bidirectional connecting to either said A first line or said B first line of each of said line pairs.
Claim 20
Dependent Claim
204 words
A programmable circuit for performing logic operations comprising: matrix having a plurality of first lines crossing a plurality of second lines to define a plurality of intersections, said first lines grouped by twos to form a plurality of line pairs, each having an A first line and a B first line; means for bidirectionally connecting each of said first lines to each of said second lines including in series a means for switching and a means for disconnecting; a plurality of first means for bidirectionally driving a signal, respectively connected to a first end of said A first line of each of said line pairs; a plurality of second means for driving a signal, respectively connected to a first end of said B first line of each of said line pairs; and means for supplying a voltage to second ends of said first and second lines; wherein for performing a selected logic operation predetermined ones of said means for bidirectional connecting are deactivated by their respective means for disconnecting such that each of said second lines is connected by predetermined others of said means for bidirectional connecting to either said A first line or said B first line of each of said line pairs.
Claim 21
Dependent Claim
128 words
A programmable circuit according to claim 18, wherein said means for bidirectional connecting comprises first and second switch elements connected in anti-parallel fashion, said first switch element being rendered non-conductive in response to a first control signal and said second control being rendered non-conductive in response to a second control signal; and wherein said first means for bidirectionally driving a signal comprises first and second drive sections connected in anti-parallel fashion, said first driver section being connected in circuit in response to said first control signal and said second driver section being connected in circuit in response to said second control signal; and wherein said first and second control signals determine if each of said line pairs functions as an input or as an output of said matrix.
Claim 22
Dependent Claim
84 words
A programmable circuit according to claim 19, wherein said first switch element is non-inverting, said second switch element is inverting, said first driver section is non-inverting and said second driver section is inverting, said first and second control signals activating said first switch elements and said first driver sections for a line pair to function as an input to said matrix and activating said second switch elements and said second driver section for a line pair to function as an output of said matrix.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |