EP0096225A2
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EP
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Interlaced programmable logic array having shared elements
Assignee: International Business Machines Corp
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Filing: 1983-05-06
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Granted: —
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Expires: 2003-05-06
Abstract
Abstract A programmable PLA circuit in which an interlaced AND/OR array (30, 32, 34) is provided which has both common input (16) and common output lines (36). Separate AND and OR functions are generated during two different timing intervals (D1, D2) such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits (40) during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval (D1) and to provide the Exclusive-NOR of sums of product terms or the sum of the Exclusive-NOR of product terms during the second time interval (D2).
Inventors
- 👤 Howard Leo Kalter
- 👤 Francis Walter Wiedman
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 15:05
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5057; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
174 words
In a programmable logic array circuit including a first logic array (30, 32) responsive to first input signals for providing first output signals corresponding to the logical product terms of selected input signals during a first time interval (Dl) and a second logic array (30, 34) responsive to second input signals to provide during a second time interval (D2) output signals corresponding to sums of selected product terms provided by the first logic array, each logic array including a plurality of input lines (16) and a plurality of output lines (36), the improvement characterized in that the input lines of both of the first and second logic arrays are physically common and the output lines of both the first and second logic arrays are physically common, said programmable logic array circuit including connecting logic means (20, 40, 50) for providing logical representations of the logical product terms generated by the first logic array to the common input lines to generate a sum of product terms on the output lines during the second time interval.
Claim 2
Dependent Claim
174 words
In a programmable logic array circuit including a first logic array (30, 32) responsive to first input signals for providing first output signals corresponding to the logical product terms of selected input signals during a first time interval (Dl) and a second logic array (30, 34) responsive to second input signals to provide during a second time interval (D2) output signals corresponding to sums of selected product terms provided by the first logic array, each logic array including a plurality of input lines (16) and a plurality of output lines (36), the improvement characterized in that the input lines of both of the first and second logic arrays are physically common and the output lines of both the first and second logic arrays are physically common, said programmable logic array circuit including connecting logic means (20, 40, 50) for providing logical representations of the logical product terms generated by the first logic array to the common input lines to generate a sum of product terms on the output lines during the second time interval.
Claim 3
Dependent Claim
80 words
The programmable logic array circuit of Claim 1 wherein the connecting logic means (20, 40, 50) includes a plurality of logical circuits (40) coupled to selected ones of the output lines for performing a predetermined logic function on at least some of the first output signals during the first time interval (Dl) and for performing the predetermined logic function on at least some of the second output signals provided on the same output lines during the second time interval (D2).
Claim 4
Dependent Claim
19 words
The programmable logic array circuit of Claim 2 wherein the predetermined logic function is that of the Exclusive-OR function.
Claim 5
Dependent Claim
19 words
The programmable logic array circuit of Claim 2 wherein the predetermined logic function is that of the Exclusive-NOR function.
Claim 6
Dependent Claim
52 words
The programmable logic array circuit of Claim 1 wherein the connecting logic means (20, 40, 50) includes first logical NOR circuitry for providing a first logical NOR function of a first group of product term-containing signals for application to the input lines of the second logic array during the second time interval.
Claim 7
Dependent Claim
50 words
The programmable logic array circuit of Claim 5 wherein the connecting logic means (20, 40, 50) further includes second logical NOR circuitry for providing a second logical NOR function of the same product term-containing signals as the first logical NOR circuitry and of a different group of product term-containing signals.
Claim 8
Dependent Claim
24 words
The programmable logic array circuit of Claim 1 wherein the first and second logic arrays (30, 32, 34) comprise a plurality of NOR circuits.
Claim 9
Dependent Claim
132 words
A programmable logic array circuit for implementing the binary addition of a pair of binary n-bit numbers in which pairs of input bits are decoded to provide simple binary addition logical functions which are applied as inputs to a logical AND array (30, 32) to provide a plurality of product terms, characterized in that selected pairs of product terms are applied to Exclusive-NOR circuits (40) the outputs of selected ones of which are, in turn, applied to NOR circuits (20,50) to generate inputs for a logical OR array (30, 34) to provide a plurality of sum terms, which, in turn, are selectively applied to the Exclusive-NOR (40) circuits, the outputs of which represent at least some of the output bits of the sum of the pair of binary numbers to be added.
Claim 10
Dependent Claim
132 words
A programmable logic array circuit for implementing the binary addition of a pair of binary n-bit numbers in which pairs of input bits are decoded to provide simple binary addition logical functions which are applied as inputs to a logical AND array (30, 32) to provide a plurality of product terms, characterized in that selected pairs of product terms are applied to Exclusive-NOR circuits (40) the outputs of selected ones of which are, in turn, applied to NOR circuits (20,50) to generate inputs for a logical OR array (30, 34) to provide a plurality of sum terms, which, in turn, are selectively applied to the Exclusive-NOR (40) circuits, the outputs of which represent at least some of the output bits of the sum of the pair of binary numbers to be added.
Claim 11
Dependent Claim
62 words
The programmable logic array circuit of Claim 8 wherein the product terms and sum terms are applied to at least some of the same Exclusive-NOR circuits (40) during two different time intervals (Dl, D2), the outputs of which are provided to the NOR circuits (20, 50) during a first time interval (Dl) and to output circuits during a second time interval (D2).
Claim 12
Dependent Claim
24 words
The programmable logic array circuit of Claim 9 wherein the AND and the OR array (30, 32, 34) are implemented as logical NOR circuits.
References Cited (Backward Citations)
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