Programmable function unit as parallel multiplier cell

Claim 2

An integrated circuit including a field programmable gate array (FPGA) which includes a programmable function unit (PFU), the programmable function unit comprising: an input line; an output line; and a programmable element for generating at least first and second functions in response to a configuration bit stream, in which the input line provides a control line to the programmable element when the first function is generated, and the input line provides a data line to the programmable element when the second function is generated; and wherein the programmable element is a look-up table.

Claim 3

The integrated circuit of claim 1 in which the first and second functions are different logic functions.

Claim 4

The integrated circuit of claim 2, in which the first function is an adder/subtracter and the control line provides the programmable element with a control signal for selecting between addition and subtraction, and the second function is an AND gate coupled to an adder and the data line provides the programmable element with a data bit.

Claim 5

The integrated circuit of claim 3 in which the AND gate coupled to the adder provides a single cell for a parallel multiplier implemented by the field programmable gate array.

Claim 6

An integrated circuit including a field programmable gate array (FPGA), the field programmable gate array including a plurality of programmable function unit (PFUs) and a programmable interconnection network for selectively coupling the programmable function units, in which at least one programmable function unit comprises: a plurality of input lines; a plurality of output lines; and a look-up table (LUT) for generating a selected one of a plurality of functions including first and second functions in response to a configuration bit stream, in which the first input line provides a control signal to the look-up table when the first function is generated, and the first input line provides a data signal to the look-up table when the second function is generated.

Claim 7

An integrated circuit including a field programmable gate array (FPGA), the field programmable gate array including a plurality of programmable function unit (PFUs) and a programmable interconnection network for selectively coupling the programmable function units, in which at least one programmable function unit comprises: a plurality of input lines; a plurality of output lines; and a look-up table (LUT) for generating a selected one of a plurality of functions including first and second functions in response to a configuration bit stream, in which the first input line provides a control signal to the look-up table when the first function is generated, and the first input line provides a data signal to the look-up table when the second function is generated.

Claim 8

The integrated circuit of claim 1, in which the programmable function unit provides an adder/subtracter and the control signal selects between addition and subtraction when the first function is generated, and the programmable function unit provides a cell including an AND gate coupled to a full-adder for use in a parallel multiplier implemented by the field programmable gate array when the second function is generated.

Claim 9

An integrated circuit including a field programmable gate array (FPGA), the field programmable gate array including a plurality of programmable function unit (PFUs) and a programmable interconnection network for selectively coupling the programmable function units, the programmable function units and interconnection network programmable by a configuration bit stream, in which at least one programmable function unit comprises: a plurality of input lines including first, second, third and fourth input lines; a plurality of output lines including first and second output lines; and a look-up table (LUT) for generating a selected one of a plurality of functions, including first and second functions, between selected input and output lines, in response to the configuration bit stream; such that when the first function is generated, the look-up table implements an adder/subtracter with the first input line receiving a control signal which selects between addition and subtraction, the second input line receiving a carry-in bit, the third input line receiving a data bit from a first data signal, the fourth input line receiving a data bit from a second data signal, the first output line providing a sum bit, and the second output line providing a carry-out bit; and such that when the second function is generated, the look-up table implements a single cell for a parallel multiplier configured to multiply a third data signal by a fourth data signal, with the first input line receiving a data bit from the third data signal, the second input line receiving the carry-in bit, the third input line receiving a data bit from a partial-product, the fourth input line receiving a data bit from the fourth data signal, the first output line providing the sum bit, and the second output line providing the carry-out bit.

Claim 10

An integrated circuit including a field programmable gate array (FPGA), the field programmable gate array including a plurality of programmable function unit (PFUs) and a programmable interconnection network for selectively coupling the programmable function units, the programmable function units and interconnection network programmable by a configuration bit stream, in which at least one programmable function unit comprises: a plurality of input lines including first, second, third and fourth input lines; a plurality of output lines including first and second output lines; and a look-up table (LUT) for generating a selected one of a plurality of functions, including first and second functions, between selected input and output lines, in response to the configuration bit stream; such that when the first function is generated, the look-up table implements an adder/subtracter with the first input line receiving a control signal which selects between addition and subtraction, the second input line receiving a carry-in bit, the third input line receiving a data bit from a first data signal, the fourth input line receiving a data bit from a second data signal, the first output line providing a sum bit, and the second output line providing a carry-out bit; and such that when the second function is generated, the look-up table implements a single cell for a parallel multiplier configured to multiply a third data signal by a fourth data signal, with the first input line receiving a data bit from the third data signal, the second input line receiving the carry-in bit, the third input line receiving a data bit from a partial-product, the fourth input line receiving a data bit from the fourth data signal, the first output line providing the sum bit, and the second output line providing the carry-out bit.

Claim 11

The integrated circuit of claim 7, in which when the first function is generated, the look-up table implements a multiplexer coupled by an internal line to a full-adder, such that when the control signal selects addition then the multiplexer couples the data bit from the first data signal through the internal line to the full-adder, and when the control signal selects subtraction then the multiplexer couples a complement of the data bit from the first data signal through the internal line to the full-adder, and when the second function is generated the look-up table implements an AND gate coupled by the internal line to the full-adder, such that the AND gate couples a product of the data bit from the third data signal and the data bit of the fourth data signal through the internal line to the full-adder.

Claim 12

The integrated circuit of claim 8 in which full-adder adds the carry-in bit to a bit at the third input line and to a bit at the internal line to produce the sum bit and the carry-out bit.

Claim 13

The integrated circuit of claim 9 in which the look-up table is coupled to a RAM cell in the field programmable gate array, and a value of a particular bit determined by the configuration bit stream and stored in the RAM cell instructs the look-up table to select one of the first and second functions.

Claim 14

An integrated circuit including a field programmable gate array (FPGA), the field programmable gate array including a plurality of programmable function unit (PFUs) and a programmable interconnection network for selectively coupling the programmable function units, the programmable function units and interconnection network programmable by a configuration bit stream applied to the field programmable gate array, in which at least one programmable function unit comprises: a plurality of input lines including first, second, third and fourth input lines; a plurality of output lines including first and second output lines; and a look-up table (LUT) for generating a selected one of a plurality of functions, including first and second functions, between selected input and output lines, in response to the configuration bit stream; the first function providing a multiplexer coupled to a full-adder for providing addition and subtraction; the second function providing an AND gate coupled to the full-adder for providing a single cell of a parallel multiplier.

Claim 15

An integrated circuit including a field programmable gate array (FPGA), the field programmable gate array including a plurality of programmable function unit (PFUs) and a programmable interconnection network for selectively coupling the programmable function units, the programmable function units and interconnection network programmable by a configuration bit stream applied to the field programmable gate array, in which at least one programmable function unit comprises: a plurality of input lines including first, second, third and fourth input lines; a plurality of output lines including first and second output lines; and a look-up table (LUT) for generating a selected one of a plurality of functions, including first and second functions, between selected input and output lines, in response to the configuration bit stream; the first function providing a multiplexer coupled to a full-adder for providing addition and subtraction; the second function providing an AND gate coupled to the full-adder for providing a single cell of a parallel multiplier.

Claim 16

The integrated circuit of claim 11, in which the look-up table generates the first and second functions by implementing a logic circuit coupled to a full-adder, the full adder receiving a first input from the third input line, a second input from the second input line, and a third input from the logic circuit, the full-adder sending a first output representing a sum bit to the first output line, and a second output representing a carry-out bit to the second output line.

Claim 17

The integrated circuit of claim 12, in which the logic circuit consists essentially of a first transistor, a second transistor, a third transistor, a fourth transistor, a first inverter, a second inverter, and a third inverter, in which the first input line is connected to a gate of the first transistor and to a drain of the fourth transistor, the fourth input line is connected to a drain of the first transistor, the third input of the full-adder is connected to a source of the first transistor and to a source of the second transistor, the first inverter is connected between the first input line and a gate of the second transistor, the second inverter is connected between the fourth input line and a drain of the third transistor, the third inverter is connected between a RAM cell of the field programmable gate array and a gate of the third transistor, a gate of a fourth transistor is connected to the RAM cell, and a drain of the second transistor is connected to a source of the third transistor and to a source of the fourth transistor.

Claim 18

An integrated circuit including a field programmable gate array (FPGA), the field programmable gate array including a plurality of programmable function unit (PFUs) and a programmable interconnection network for selectively coupling the programmable function units, the programmable function units and network being programmable by a configuration bit stream, comprising: a set of the programmable function units programmable to provide a parallel multiplier in which each programmable function unit in the set provides a single cell for the parallel multiplier, wherein each programmable function unit in the set is programmable to include the function of an AND gate coupled to a full-adder, with a first input line for coupling a data signal to the AND gate.

Claim 19

An integrated circuit including a field programmable gate array (FPGA), the field programmable gate array including a plurality of programmable function unit (PFUs) and a programmable interconnection network for selectively coupling the programmable function units, the programmable function units and network being programmable by a configuration bit stream, comprising: a set of the programmable function units programmable to provide a parallel multiplier in which each programmable function unit in the set provides a single cell for the parallel multiplier, wherein each programmable function unit in the set is programmable to include the function of an AND gate coupled to a full-adder, with a first input line for coupling a data signal to the AND gate.

Claim 20

The integrated circuit of claim 14 in which each programmable function unit in the set is also programmable to include the function of a multiplexer coupled to the full-adder, with the first input line for coupling a control signal to the multiplexer for selectively coupling one of a data bit and its complement to the full-adder.

Claim 25

The method of claim 17, in which the first and second programmable function units each comprise a plurality of input lines and output lines, the input lines including a first input line, the first input line of the first programmable function unit coupled to a first input of the AND gate for receiving a first data bit, and the first input line of the second programmable function unit coupled to the multiplexer for receiving a control signal to determine whether a second data bit or its complement is coupled to the full-adder.

Claim 26

The method of claim 17 in which the first and second portions of the configuration bit stream differ from one another by a value of a single bit

Claim 29

The method of claim 20 with each programmable function unit in the set functioning as both an AND gate and a full-adder.

Claim 32

An integrated circuit including a field programmable gate array (FPGA) which includes a programmable function unit (PFU), the programmable function unit comprising: an input line; an output line; and a programmable element for generating at least first and second functions in response to a configuration bit stream, in which the input line provides a control line to the programmable element when the first function is generated, and the input line provides a data line to the programmable element when the second function is generated; and wherein the first and second functions are different logic functions.

Claim 33

An integrated circuit including a field programmable gate array (FPGA) which includes a programmable function unit (PFU), the programmable function unit comprising: an input line; an output line; and a programmable element for generating at least first and second functions in response to a configuration bit stream, in which the input line provides a control line to the programmable element when the first function is generated, and the input line provides a data line to the programmable element when the second function is generated; and wherein the first and second functions are different logic functions.

Claim 34

The integrated circuit of claim 23 in which the programmable element is a look-up table.

Claim 35

The integrated circuit of claim 23 in which the first function is an adder/subtracter and the control line provides the programmable element which a control signal for selecting between addition and subtraction, and the second function is an AND gate coupled to an adder and the data line provides the programmable element with a data bit.

Claim 36

The integrated circuit of claim 25 in which the AND gate coupled to the adder provides a single cell for a parallel multiplier implemented by the field programmable gate array.