US6154049A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiplier fabric for use in field programmable gate arrays
Assignee: Xilinx Inc
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Filing: 1998-03-27
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Granted: 2000-11-28
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Expires: 2018-03-27
Abstract
Abstract A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of multiplier tiles. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the array of multiplier tiles. However, selected CLEs can also be coupled to selected multiplier tiles, thereby creating a relatively high density multiplier circuit. Each of the multiplier tiles includes a multiplier array having a predetermined size (e.g., a 2×4 bit multiplier array). The multiplier tiles can be selectively coupled to one another, such that the multiplier arrays are connected to form a relatively large multiplier circuit. The desired multiplier and multiplicand bits are routed into the multiplier tiles from associated CLEs. Similarly, the resulting product bits are routed from the multiplier tiles to associated CLEs. In this manner, the FPGA is capable of implementing a relatively large multiplier circuit in an efficient manner.
Inventors
- 👤 Bernard J. New
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:11
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5324; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17724; H03K19/17728; H03K19/17732; H03K19/17736
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
36 words
A programmable logic device comprising: an array of configurable logic elements (CLEs); an array of multiplier tiles; and programmable interconnect resources for selectively coupling each multiplier tile to an associated CLE and to adjacent multiplier tiles.
Claim 2
Dependent Claim
36 words
A programmable logic device comprising: an array of configurable logic elements (CLEs); an array of multiplier tiles; and programmable interconnect resources for selectively coupling each multiplier tile to an associated CLE and to adjacent multiplier tiles.
Claim 3
Dependent Claim
17 words
The programmable logic device of claim 1, further comprising programmable interconnect resources for selectively coupling the CLES.
Claim 4
Dependent Claim
30 words
The programmable logic device of claim 1, wherein each of the multiplier tiles comprises a plurality of adder circuits arranged in at least one column and at least one row.
Claim 5
Dependent Claim
20 words
The programmable logic device of claim 3, further comprising a logical AND gate coupled to each of the adder circuits.
Claim 6
Dependent Claim
20 words
The programmable logic device of claim 3, wherein at least one of the adder circuits also supports a subtractor functionality.
Claim 7
Dependent Claim
30 words
The programmable logic device of claim 1, wherein the programmable interconnect resources comprise a plurality of programmable multiplexers for selectively connecting or isolating each multiplier tile from an associated CLE.
Claim 8
Dependent Claim
26 words
The programmable logic device of claim 1, wherein the programmable interconnect resources comprise a plurality of programmable multiplexers for selectively connecting or isolating adjacent multiplier tiles.
Claim 9
Dependent Claim
27 words
The programmable logic device of claim 1, wherein the programmable interconnect resources selectively interconnect a plurality of multiplier tiles to form at least one larger multiplier circuit.
Claim 10
Dependent Claim
31 words
The programmable logic device of claim 1, wherein the programmable interconnect resources selectively propagate one or both of a sum signal and a carry signal between a plurality of multiplier tiles.
Claim 11
Dependent Claim
55 words
The programmable logic device of claim 1, wherein each of the multiplier tiles comprises: a first plurality of multiplexers for selectively routing multiplier bits from an adjacent multiplier tile or from an associated CLE; and a second plurality of multiplexers for selectively routing multiplicand bits from an adjacent multiplier tile or from an associated CLE.
Claim 12
Dependent Claim
14 words
The programmable logic device of claim 1, wherein the multiplier tiles support unsigned multiplication.
Claim 13
Dependent Claim
14 words
The programmable logic device of claim 11, wherein the multiplier tiles support signed multiplication.
Claim 14
Dependent Claim
23 words
The programmable logic device of claim 1, wherein each of the CLEs comprises: a programmable function generator; and a programmable carry logic circuit.
Claim 15
Dependent Claim
17 words
The programmable logic device of claim 1, wherein the multiplier tiles are configured to perform carry-propagate multiplication.
Claim 16
Dependent Claim
17 words
The programmable logic device of claim 1, wherein the multiplier tiles are configured to perform carry-save multiplication.
Claim 17
Dependent Claim
24 words
The programmable logic device of claim 15, wherein each of the CLEs comprises adder circuitry for adding signals generated by an associated multiplier tile.
Claim 18
Independent Claim
120 words
A method of operating a programmable logic device, the method comprising the steps of: providing an array of configurable logic elements (CLEs) and an array of multiplier tiles; selectively coupling a first set of the multiplier tiles to form a multiplier circuit; coupling a first subset of multiplier tiles within the first set of multiplier tiles to a first subset of associated CLES; routing multiplier signals and multiplicand signals from the first subset of CLEs to the first subset of multiplier tiles; coupling a second subset of multiplier tiles within the first set of multiplier tiles to a second subset of associated CLEs; and routing product signals from the second subset of multiplier tiles to the second subset of CLEs.
Claim 19
Independent Claim
120 words
A method of operating a programmable logic device, the method comprising the steps of: providing an array of configurable logic elements (CLEs) and an array of multiplier tiles; selectively coupling a first set of the multiplier tiles to form a multiplier circuit; coupling a first subset of multiplier tiles within the first set of multiplier tiles to a first subset of associated CLES; routing multiplier signals and multiplicand signals from the first subset of CLEs to the first subset of multiplier tiles; coupling a second subset of multiplier tiles within the first set of multiplier tiles to a second subset of associated CLEs; and routing product signals from the second subset of multiplier tiles to the second subset of CLEs.
Claim 20
Dependent Claim
25 words
The method of claim 17, further comprising the step of multiplying an unsigned multiplier and an unsigned multiplicand within the first set of multiplier tiles.
Claim 21
Dependent Claim
25 words
The method of claim 17, further comprising the step of multiplying a signed multiplier and an unsigned multiplicand within the first set of multiplier tiles.
Claim 22
Dependent Claim
25 words
The method of claim 17, further comprising the step of multiplying a signed multiplier and a signed multiplicand within the first set of multiplier tiles.
Claim 23
Dependent Claim
25 words
The method of claim 17, further comprising the step of multiplying a unsigned multiplier and a signed multiplicand within the first set of multiplier tiles.
Claim 24
Dependent Claim
22 words
The method of claim 17, further comprising the step of performing a carry-propagate multiplication operation within the first set of multiplier tiles.
Claim 25
Dependent Claim
22 words
The method of claim 17, further comprising the step of performing a carry-save multiplication operation within the first set of multiplier tiles.
Claim 26
Dependent Claim
27 words
The method of claim 23, further comprising the step of adding carry and save signals generated by the carry-save multiplication operation within the second subset of CLEs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |