Method and structure for providing fast conditional sum in a field programmable gate array

Claim 1

A field programmable gate array (FPGA) having at least one carry logic circuit including first and second carry chains, said carry logic circuit comprising: at least one carry chain stage including a first carry chain stage generating the carry of two input bits and a carry-in bit from a less significant stage in said first carry chain, and a second carry chain stage generating the carry of said two input bits and a carry-in bit from a less significant stage in said second carry chain; two conditional sum generating means, a first conditional sum generating means generating a first conditional sum from said two input bits and said carry-in bit in said first carry chain, and a second conditional sum generating means generating a second conditional sum from said two input bits and said carry-in bit in said second carry chain; means for selecting between said first and second carry chains based on a carry logic circuit carry-in signal; and means for selecting between said first and second conditional sums based on said carry logic circuit carry-in signal.