Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor

Claim 2

An active matrix device comprising: a substrate; a thin film transistor formed over said substrate, said thin film transistor comprising a crystalline semiconductor film including at least source, drain and channel regions; a first electrode formed over said substrate; a first interlayer insulating film formed over said first electrode, said first interlayer insulating film covering said thin film transistor; a second interlayer insulating film comprising a different material from said first interlayer insulating film formed on said first interlayer insulating film; an opening selectively formed in said second interlayer insulating film to expose a surface of said first interlayer insulating film therein; a second electrode formed on said first interlayer insulating film in said opening and a capacitor formed between said first and second electrodes in said opening with at least said first interlayer insulating film interposed therebetween.

Claim 3

An active matrix device according to claim 1 wherein said second electrode extends on a portion of said second interlayer insulating film.

Claim 4

An active matrix device according to claim 1 wherein said first interlayer insulating film comprises silicon oxide.

Claim 5

An active matrix device according to claim 1 wherein said second interlayer insulating film comprises silicon nitride.

Claim 6

An active matrix device according to claim 1 wherein said active matrix device is a liquid crystal display device.

Claim 7

An active matrix device comprising: a substrate; a thin film transistor formed over said substrate, said thin film transistor including at least source, drain and channel regions; a first electrode formed over said substrate; a first interlayer insulating film formed over said first electrode, said first interlayer insulating film covering said thin film transistor; a second interlayer insulating film comprising a different material from said first interlayer insulating film formed on said first interlayer insulating film; an opening selectively formed in said second interlayer insulating film to expose a surface of said first interlayer insulating film therein; a second electrode formed on said first interlayer insulating film in said opening; and a capacitor operatively connected to said thin film transistor; said first interlayer insulating film interposed therebetween.

Claim 8

An active matrix device comprising: a substrate; a thin film transistor formed over said substrate, said thin film transistor including at least source, drain and channel regions; a first electrode formed over said substrate; a first interlayer insulating film formed over said first electrode, said first interlayer insulating film covering said thin film transistor; a second interlayer insulating film comprising a different material from said first interlayer insulating film formed on said first interlayer insulating film; an opening selectively formed in said second interlayer insulating film to expose a surface of said first interlayer insulating film therein; a second electrode formed on said first interlayer insulating film in said opening; and a capacitor operatively connected to said thin film transistor; said first interlayer insulating film interposed therebetween.

Claim 9

An active matrix device according to claim 6 wherein said first interlayer insulating film comprises silicon oxide.

Claim 10

An active matrix device according to claim 6 wherein said second interlayer insulating film comprises silicon nitride.

Claim 11

An active matrix device according to claim 6 wherein said second electrode is electrically connected to one of said source and drain regions of said thin film transistor.

Claim 12

An active matrix device according to claim 6 further comprising a third interlayer insulating film between said first electrode and said thin film transistor.

Claim 13

An active matrix device according to claim 6 wherein said second electrode extends on a portion of said second interlayer insulating film.

Claim 14

An active matrix device according to claim 6 wherein said active matrix device is a liquid crystal display device.

Claim 15

An active matrix device comprising: a substrate; a thin film transistor formed over said substrate, said thin film transistor comprising a crystallline semiconductor film including at least source, drain and channel regions; a first electrode formed over said substrate; a first interlayer insulating film formed over said first electrode said first interlayer insulating film covering said thin film transistor; a second interlayer insulating film comprising a different material from said first interlayer insulating film formed on said first interlayer insulating film; an opening selectively formed in said second interlayer insulating film to expose a surface of said first interlayer insulating film therein; a pixel electrode electrically connected to one of said source end drain regions of said thin film transistor, said pixel electrode formed on said second interlayer insulating film and extend into said opening; and a capacitor formed between said first electrode and said pixel electrode in said opening with at least said first interlayer insulating film interposed therebetween.

Claim 16

An active matrix device comprising: a substrate; a thin film transistor formed over said substrate, said thin film transistor comprising a crystallline semiconductor film including at least source, drain and channel regions; a first electrode formed over said substrate; a first interlayer insulating film formed over said first electrode said first interlayer insulating film covering said thin film transistor; a second interlayer insulating film comprising a different material from said first interlayer insulating film formed on said first interlayer insulating film; an opening selectively formed in said second interlayer insulating film to expose a surface of said first interlayer insulating film therein; a pixel electrode electrically connected to one of said source end drain regions of said thin film transistor, said pixel electrode formed on said second interlayer insulating film and extend into said opening; and a capacitor formed between said first electrode and said pixel electrode in said opening with at least said first interlayer insulating film interposed therebetween.

Claim 17

An active matrix device according to claim 13 wherein said first interlayer insulating film comprises silicon oxide.

Claim 18

An active matrix device according to claim 13 wherein said second interlayer insulating film comprises silicon nitride.

Claim 19

An active matrix device according to claim 13 further comprising a third interlayer insulating film between said first electrode and said thin film transistor.

Claim 20

An active matrix device according to claim 13 further comprising a drain electrode connected to said drain of the thin film transistor, wherein said first electrode is formed in a same process as said drain electrode.

Claim 21

An active matrix device according to claim 13 wherein said first electrode is formed in a same level a gate electrode of said thin film transistor.

Claim 22

An active matrix device according to claim 13 wherein said active matrix device is a liquid crystal display device.

Claim 23

An active matrix device comprising: a substrate; a thin film transistor provided over said substrate, said thin film transistor comprising a crystalline semiconductor film, a gate electrode and a gate insulating film located between said crystalline semiconductor film and said gate electrode, wherein said crystalline semiconductor film has source and drain regions, a channel region and at least one LDD region located between one of said source and drain regions and said channel region; a first electrode formed over said substrate; a first interlayer insulating film to cover said thin film transistor, said first interlayer insulating film comprising silicon oxide; a second interlayer insulating film provided over said first interlayer insulating film, said second interlayer insulating film compnising silicon nitride; an opening selectively formed in said second interlayer insulating film to expose a surface of said first interlayer insulating film therein; a pixel electrode provided on said first interlaver insulating film in said opening; and a capacitor formed between said first electrode and said pixel electrode in said opening with at least said first interlaver insulating film interposed therebetween, wherein a boundary between said LDD region and said channel region is aligned with a side edge of said gate electrode.

Claim 24

An active matrix device comprising: a substrate; a thin film transistor provided over said substrate, said thin film transistor comprising a crystalline semiconductor film, a gate electrode and a gate insulating film located between said crystalline semiconductor film and said gate electrode, wherein said crystalline semiconductor film has source and drain regions, a channel region and at least one LDD region located between one of said source and drain regions and said channel region; a first electrode formed over said substrate; a first interlayer insulating film to cover said thin film transistor, said first interlayer insulating film comprising silicon oxide; a second interlayer insulating film provided over said first interlayer insulating film, said second interlayer insulating film compnising silicon nitride; an opening selectively formed in said second interlayer insulating film to expose a surface of said first interlayer insulating film therein; a pixel electrode provided on said first interlaver insulating film in said opening; and a capacitor formed between said first electrode and said pixel electrode in said opening with at least said first interlaver insulating film interposed therebetween, wherein a boundary between said LDD region and said channel region is aligned with a side edge of said gate electrode.

Claim 25

An active matrix device according to claim 20 wherein said pixel electrode comprises indium tin oxide.

Claim 26

An active matrix device according to claim 20 wherein said thin film transistor is an n-channel type.

Claim 27

An active matrix device according to claim 20 wherein said gate electrode is located over said semiconductor film.

Claim 28

An active matrix device according to claim 20 wherein said active matrix device is a liquid crystal display device.

Claim 29

An active matrix device comprising: a substrate; a thin film transistor provided over said substrate, said thin film transistor comprising a crystalline semiconductor film, a gate electrode and a gate insulating film located between said crystalline semiconductor film and said gate electrode; a first interlayer insulating film to cover said thin film transistor; a wiring provided on said first interlayer insulating film; a second interlayer insulating film provided on said first interlayer insulating film; a third interlayer insulating film provided on said second interlayer insulating film, said third interlayer insulating film having an opening to expose a surface of said second interlayer insulating film; a pixel electrode provided on said third interlayer insulating film; and a capacitor provided between said wiring and said pixel electrode in said opening with said second interlayer insulating film interposed therebetween, wherein said crystalline semiconductor film comprises a pair of impurity regions and a channel region located between said pair of impurity regions, said pair of impurity regions comprises an n-type impurity, and wherein said third interlayer insulating film comprises a different material from said first and second interlayer insulating films.

Claim 30

An active matrix device comprising: a substrate; a thin film transistor provided over said substrate, said thin film transistor comprising a crystalline semiconductor film, a gate electrode and a gate insulating film located between said crystalline semiconductor film and said gate electrode; a first interlayer insulating film to cover said thin film transistor; a wiring provided on said first interlayer insulating film; a second interlayer insulating film provided on said first interlayer insulating film; a third interlayer insulating film provided on said second interlayer insulating film, said third interlayer insulating film having an opening to expose a surface of said second interlayer insulating film; a pixel electrode provided on said third interlayer insulating film; and a capacitor provided between said wiring and said pixel electrode in said opening with said second interlayer insulating film interposed therebetween, wherein said crystalline semiconductor film comprises a pair of impurity regions and a channel region located between said pair of impurity regions, said pair of impurity regions comprises an n-type impurity, and wherein said third interlayer insulating film comprises a different material from said first and second interlayer insulating films.

Claim 31

An active matrix device according to claim 25 wherein said first interlayer insulating film comprises silicon oxide.

Claim 32

An active matrix device according to claim 25 wherein said pixel electrode comprises indium tin oxide.

Claim 33

An active matrix device according to claim 25 wherein said ntype impurity is phosphorus.

Claim 34

An active matrix device according to claim 25 wherein said active matrix device is a liquid crystal display device.

Claim 35

An active matrix device comprising: a substrate; a thin film transistor provide over said substrate, said thin film transistor comprising a crystalline semiconductor film, a gate electrode and a gate insulating film located between said crystalline semiconductor film and said gate electrode, wherein said crystalline semiconductor film has source and drain regions, a channel region and at least one LDD region located between one of said source and drain regions and said channel region; a wiring provided over said substrate; a first interlayer insulating film to cover said thin film transistor and said wiring; a second interlayer insulating film provided over said first interlayer insulating film; an opening selectively formed through said second interlayer insulating film to expose a surface of said first interlayer insulating film; an electrode provided over said second interlayer insulating film, said electrode being in contact with said first interlayer insulating film in said opening; and a capacitor operatively connected to said thin film transistor, said capacitor provided between said wiring and said electrode in said opening with said first interlayer insulating film interposed therebetween, wherein said first interlayer insulating film comprises a different material from said second interlayer insulating film, and wherein a boundary between said LDD region and said channel region is aligned with a side edge of said gate electrode.

Claim 36

An active matrix device comprising: a substrate; a thin film transistor provide over said substrate, said thin film transistor comprising a crystalline semiconductor film, a gate electrode and a gate insulating film located between said crystalline semiconductor film and said gate electrode, wherein said crystalline semiconductor film has source and drain regions, a channel region and at least one LDD region located between one of said source and drain regions and said channel region; a wiring provided over said substrate; a first interlayer insulating film to cover said thin film transistor and said wiring; a second interlayer insulating film provided over said first interlayer insulating film; an opening selectively formed through said second interlayer insulating film to expose a surface of said first interlayer insulating film; an electrode provided over said second interlayer insulating film, said electrode being in contact with said first interlayer insulating film in said opening; and a capacitor operatively connected to said thin film transistor, said capacitor provided between said wiring and said electrode in said opening with said first interlayer insulating film interposed therebetween, wherein said first interlayer insulating film comprises a different material from said second interlayer insulating film, and wherein a boundary between said LDD region and said channel region is aligned with a side edge of said gate electrode.

Claim 37

An active matrix device according to claim 30 wherein said first interlayer insulating film comprises silicon oxide.

Claim 38

An active matrix device according to claim 30 wherein said second interlayer insulating film comprises silicon nitride.

Claim 39

An active matrix device according to claim 30 wherein said wiring comprises aluminum.

Claim 40

An active matrix device according to claim 30 wherein said electrode comprises indium tin oxide.

Claim 41

An active matrix device according to claim 30 wherein said thin film transistor is an n-channel type.

Claim 42

An active matrix device according to claim 30 wherein said gate electrode is located over said semiconductor film.

Claim 43

An active matrix device according to claim 30 wherein said active matrix device is a liquid crystal display device.

Claim 44

An active matrix device comprising: a substrate; a thin film transistor provided over said substrate, said thin film transistor comprising a semiconductor film, a gate electrode and a gate insulating film located between said semiconductor film and said gate electrode, wherein said semiconductor film has source and drain regions, a channel region and at least one LDD region located between one of said source and drain regions and said channel region; a first interlayer insulating film provided to cover said thin film transistor; a wiring provided on said first interlayer insulating film; a second interlayer insulating film provided on said first interlayer insulating film and said wiring; a third interlayer insulating film provided on said second interlayer insulating film, said third interlayer insulating film having an opening to expose a surface of said second interlayer insulating film; an electrode provided on said third interlayer insulating film, said electrode being in contact with said second interlayer insulating film in said opening; and a capacitor operatively connected to said thin film transistor, said capacitor provided between said wiring and said electrode in said opening with said second interlayer insulating film interposed therebetween, wherein said third interlayer insulating film comprises a different material from said second interlayer insulating film.

Claim 45

An active matrix device comprising: a substrate; a thin film transistor provided over said substrate, said thin film transistor comprising a semiconductor film, a gate electrode and a gate insulating film located between said semiconductor film and said gate electrode, wherein said semiconductor film has source and drain regions, a channel region and at least one LDD region located between one of said source and drain regions and said channel region; a first interlayer insulating film provided to cover said thin film transistor; a wiring provided on said first interlayer insulating film; a second interlayer insulating film provided on said first interlayer insulating film and said wiring; a third interlayer insulating film provided on said second interlayer insulating film, said third interlayer insulating film having an opening to expose a surface of said second interlayer insulating film; an electrode provided on said third interlayer insulating film, said electrode being in contact with said second interlayer insulating film in said opening; and a capacitor operatively connected to said thin film transistor, said capacitor provided between said wiring and said electrode in said opening with said second interlayer insulating film interposed therebetween, wherein said third interlayer insulating film comprises a different material from said second interlayer insulating film.

Claim 46

An active matrix device according to claim 38 wherein said first interlayer insulating film comprises silicon oxide.

Claim 47

An active matrix device according to claim 38 wherein said second interlayer insulating film comprises silicon oxide while said third interlayer insulating film comprises silicon nitride.

Claim 48

An active matrix device according to claim 38 wherein said electrode is a pixel electrode comprising indium tin oxide.

Claim 49

An active matrix device according to claim 38 wherein said thin film transistor is an n-channel type.

Claim 50

An active matrix device according to claim 38 wherein said gate electrode is located over said semiconductor film.

Claim 51

An active matrix device according to claim 38 wherein a boundary between said LDD region and said channel region is aligned with a side edge of said gate electrode.

Claim 52

An active matrix device according to claim 38 wherein said active matrix device is a liquid crystal display device.

Claim 53

An active matrix device comprising: a substrate; a wiring formed over said substrate; a thin film transistor provided over said substrate, said thin film transistor comprising a semiconductor film, a gate electrode and a gate insulating film located between said semiconductor film and said gate electrode, wherein said semiconductor film has a source region, a drain region, a channel region and at least one LDD region; a first interlayer insulating film to cover said thin film transistor, said first interlayer insulating film comprising silicon oxide; a second interlayer insulating film provided in contact with said first interlayer insulating film, said second interlayer insulating film comprising silicon nitride; a pixel electrode electrically connected to one of said source region and said drain region; at least one of a source electrode connected to said source region and a drain electrode connected to said drain region; and a capacitor operatively connected to said thin film transistor and provided between said wiring and said pixel electrode with at least said first interlayer film interposed therebetween.

Claim 54

An active matrix device comprising: a substrate; a wiring formed over said substrate; a thin film transistor provided over said substrate, said thin film transistor comprising a semiconductor film, a gate electrode and a gate insulating film located between said semiconductor film and said gate electrode, wherein said semiconductor film has a source region, a drain region, a channel region and at least one LDD region; a first interlayer insulating film to cover said thin film transistor, said first interlayer insulating film comprising silicon oxide; a second interlayer insulating film provided in contact with said first interlayer insulating film, said second interlayer insulating film comprising silicon nitride; a pixel electrode electrically connected to one of said source region and said drain region; at least one of a source electrode connected to said source region and a drain electrode connected to said drain region; and a capacitor operatively connected to said thin film transistor and provided between said wiring and said pixel electrode with at least said first interlayer film interposed therebetween.

Claim 55

An active matrix device according to claim 46 wherein said semiconductor film is formed of crystalline silicon.

Claim 56

An active matrix device according to claim 47 wherein said thin film transistor is an n-channel type, and said gate electrode and said at least one LDD region are not overlapped with each other.

Claim 57

An active matrix device according to claim 46 wherein said active matrix device is a liquid crystal display device.