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US6313487B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Vertical channel floating gate transistor having silicon germanium channel layer

Assignee: Liberty Patents LLC
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Filing: 2000-06-15
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Granted: 2001-11-06
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Expires: 2020-06-15
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Abstract

Abstract A vertical channel flash memory cell with a silicon germanium layer in the channel region provides enhanced secondary electron injection when programming the device. The device includes a silicon substrate, a silicon germanium alloy layer epitaxially grown on the substrate, and a silicon layer epitaxially grown on the silicon germanium layer. A sidewall through the stacked structure is formed by etching thereby exposing edges of the silicon layer and the silicon germanium layer and a portion of the substrate. A floating gate is formed overlying the sidewall and insulated therefrom with a control gate overlying the floating gate and insulated therefrom. A source region is formed in the silicon layer and a drain region is formed in the substrate with a channel therebetween along the sidewall and including the silicon germanium layer. The silicon germanium layer is preferably compressively strained and can have a uniform mole fraction or a graded mole fraction. The vertical structure permits the fabrication of flash memory cells with smaller dimensions and lower operating voltages.

Inventors

  • 👤 David L. Kencke
  • 👤 Sanjay K. Banerjee

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 20:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 132 words
A field effect transistor comprising: a) a silicon substrate, b) an epitaxial silicon germanium layer grown on a surface of the substrate, c) an epitaxial silicon layer grown on a surface of the silicon germanium layer, d) a sidewall exposing the silicon layer, the silicon germanium layer, and a portion of the substrate, e) a first gate dielectric formed on the sidewall, f) a floating gate formed on the first gate dielectric over the sidewall, g) a second gate dielectric formed over the floating gate, h) a control gate formed on the second gate dielectric and over the control gate, i) a source region formed in the epitaxial silicon layer, and j) a drain region formed in the substrate, whereby a channel is provided between the source and drain along the sidewall.
Claim 2
Dependent Claim 132 words
A field effect transistor comprising: a) a silicon substrate, b) an epitaxial silicon germanium layer grown on a surface of the substrate, c) an epitaxial silicon layer grown on a surface of the silicon germanium layer, d) a sidewall exposing the silicon layer, the silicon germanium layer, and a portion of the substrate, e) a first gate dielectric formed on the sidewall, f) a floating gate formed on the first gate dielectric over the sidewall, g) a second gate dielectric formed over the floating gate, h) a control gate formed on the second gate dielectric and over the control gate, i) a source region formed in the epitaxial silicon layer, and j) a drain region formed in the substrate, whereby a channel is provided between the source and drain along the sidewall.
Claim 3
Dependent Claim 18 words
A field effect transistor as defined by claim 1 wherein the epitaxial silicon germanium layer is compressively strained.
Claim 4
Dependent Claim 20 words
A field effect transistor as defined by claim 2 wherein the epitaxial silicon germanium layer has a uniform mole fraction.
Claim 5
Dependent Claim 36 words
A field effect transistor as defined by claim 2 wherein the epitaxial silicon germanium layer has a graded mole fraction from 1−x=0 at the substrate to 1−x=a maximum value for a Si x Ge 1−x .
Claim 6
Dependent Claim 26 words
The field effect transistor as defined by claim 2 wherein the thickness of the silicon germanium layer is below a critical value to maintain pseudomorphic strain.
Claim 7
Dependent Claim 22 words
The field effect transistor as defined by claim 2 and further including: k) a silicon cap layer epitaxially grown on the sidewall.
Claim 8
Dependent Claim 18 words
The field effect transistor as defined by claim 6 wherein the epitaxial silicon germanium layer is compressively strained.
Claim 9
Dependent Claim 20 words
The field effect transistor as defined by claim 6 wherein the epitaxial silicon germanium layer has a uniform mole fraction.
Claim 10
Dependent Claim 35 words
The field effect transistor as defined by claim 6 wherein the epitaxial silicon layer has a graded mole fraction from 1−x=0 at the substrate to 1−x=a maxium value for a Si x Ge 1−x layer.
Claim 11
Dependent Claim 26 words
The field effect transistor as defined by claim 6 wherein the thickness of the silicon germanium layer is below a critical value to maintain pseudomorphic strain.
Claim 12
Dependent Claim 105 words
A vertical channel flash memory device comprising: a) a stacked silicon substrate, a silicon germanium alloy layer epitaxially grown on the substrate, and a silicon layer epitaxially grown on the silicon germanium layer, b) a sidewall through the stacked structures exposing edges of the silicon layer and silicon germanium layer and a portion of the substrate, c) a floating gate overlying the sidewall and insulated therefrom, d) a control gate overlying the floating gate and insulated therefrom, and e) a source region in the silicon layer and a drain in the substrate with a channel therebetween along the sidewall and including the silicon gemanium layer.
Claim 13
Dependent Claim 105 words
A vertical channel flash memory device comprising: a) a stacked silicon substrate, a silicon germanium alloy layer epitaxially grown on the substrate, and a silicon layer epitaxially grown on the silicon germanium layer, b) a sidewall through the stacked structures exposing edges of the silicon layer and silicon germanium layer and a portion of the substrate, c) a floating gate overlying the sidewall and insulated therefrom, d) a control gate overlying the floating gate and insulated therefrom, and e) a source region in the silicon layer and a drain in the substrate with a channel therebetween along the sidewall and including the silicon gemanium layer.
Claim 14
Dependent Claim 16 words
The device as defined by claim 11 wherein the epitaxial silicon germanium layer is compressively strained.
Claim 15
Dependent Claim 18 words
The device as defined by claim 12 wherein the epitaxial silicon germanium layer has a uniform mole fraction.
Claim 16
Dependent Claim 34 words
The device as defined by claim 12 wherein the epitaxial silicon germanium layer has a graded mole fraction from 1−x=0 at the substrate to 1−x=a maximum value for a Si x Ge 1−x layer.
Claim 17
Dependent Claim 24 words
The device as defined by claim 12 wherein the thickness of the silicon germanium layer is below a critical value to maintain pseudomorphic strain.
Claim 18
Dependent Claim 20 words
The device as defined by claim 11 and further including: k) a silicon cap layer epitaxially grown on the sidewall.
Claim 19
Dependent Claim 16 words
The device as defined by claim 16 wherein the epitaxial silicon germanium layer is compressively strained.
Claim 20
Dependent Claim 18 words
The device as defined by claim 16 wherein the epitaxial silicon germanium layer has a uniform mole fraction.
Claim 21
Dependent Claim 34 words
The device as defined by claim 16 wherein the epitaxial silicon germanium layer has a graded mole fraction from 1−x=0 at the substrate to 1−x=a maximum value for a Si x Ge 1−x layer.
Claim 22
Dependent Claim 24 words
The device as defined by claim 16 wherein the thickness of the silicon germanium layer is below a critical value to maintain pseudomorphic strain.

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Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-11-05 2005-05-07 2005-11-06 $2000.00 Window Closed / Lapsed
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