US5901084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory device having floating gate electrode
Assignee: Mitsubishi Electric Corp
•
Filing: 1997-09-23
•
Granted: 1999-05-04
•
Expires: 2017-09-23
Abstract
Abstract A nonvolatile semiconductor memory device is obtained of which tunnel oxide film can be made thinner and which can allow low voltage and power consumption. P type polycrystal silicon is used as a floating gate electrode. Thickness of a tunnel oxide film (first insulating film) is set to less than 10 nm. By using P type polysilicon as a material of the floating gate electrode, a barrier height of a well-type potential is increased from 3.1 eV to 4.4 eV, and thus the leak current is effectively prevented. Thus, the film thickness of the tunnel oxide film can be made less than 10 nm, and operating voltage can also be lowered. Therefore, reduction in power consumption and improvement in performance of the nonvolatile semiconductor memory device can be achieved.
Inventors
- 👤 Takahiro Ohnakado
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10B; H10B41/00; H10B41/30; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
146 words
A nonvolatile semiconductor memory device, comprising: a P type source region and a P type drain region formed spaced apart with a channel region therebetween, at a main surface of an N type semiconductor region; a first insulating film formed on said channel region and having a thickness of less than 10 nm; a floating gate electrode formed on said first insulating film and containing P type polycrystalline silicon; a second insulating film formed on said floating gate electrode; and a control gate electrode formed on said second insulating film, wherein an electric field of at least 10 MV/cm is applied to said first insulating film, and electrons in said floating gate electrode are extracted toward the main surface of said semiconductor region by tunnel phenomenon, whereby a writing or erasing operation is performed by increasing the amount of positive charges in said floating gate electrode.
Claim 2
Dependent Claim
146 words
A nonvolatile semiconductor memory device, comprising: a P type source region and a P type drain region formed spaced apart with a channel region therebetween, at a main surface of an N type semiconductor region; a first insulating film formed on said channel region and having a thickness of less than 10 nm; a floating gate electrode formed on said first insulating film and containing P type polycrystalline silicon; a second insulating film formed on said floating gate electrode; and a control gate electrode formed on said second insulating film, wherein an electric field of at least 10 MV/cm is applied to said first insulating film, and electrons in said floating gate electrode are extracted toward the main surface of said semiconductor region by tunnel phenomenon, whereby a writing or erasing operation is performed by increasing the amount of positive charges in said floating gate electrode.
Claim 3
Dependent Claim
19 words
The nonvolatile semiconductor memory device according to claim 1, wherein said control gate electrode contains P type polycrystalline silicon.
Claim 4
Dependent Claim
128 words
A nonvolatile semiconductor memory device, comprising: a P type source region and a P type drain region formed spaced apart with a channel region therebetween, at a main surface of an N type semiconductor region; a first insulating film formed on said channel region and having a thickness of less than 10 nm; a floating gate electrode formed on said first insulating film and containing P type polycrystalline silicon; a second insulating film formed on said floating gate electrode; and a control gate electrode formed on said second insulating film, wherein a writing or erasing operation is performed by increasing the amount of positive charges in said floating gate electrode by hot hole injection phenomenon from the main surface of said semiconductor region to said floating gate electrode.
Claim 5
Dependent Claim
128 words
A nonvolatile semiconductor memory device, comprising: a P type source region and a P type drain region formed spaced apart with a channel region therebetween, at a main surface of an N type semiconductor region; a first insulating film formed on said channel region and having a thickness of less than 10 nm; a floating gate electrode formed on said first insulating film and containing P type polycrystalline silicon; a second insulating film formed on said floating gate electrode; and a control gate electrode formed on said second insulating film, wherein a writing or erasing operation is performed by increasing the amount of positive charges in said floating gate electrode by hot hole injection phenomenon from the main surface of said semiconductor region to said floating gate electrode.
Claim 6
Dependent Claim
19 words
The nonvolatile semiconductor memory device according to claim 3, wherein said control gate electrode contains P type polycrystalline silicon.
References Cited (Backward Citations)
US3744036A
Cited
JPH0425176A
Cited
US5260593A
Cited
JPH06125089A
Cited
JPH07169861A
Cited
US5650649A
Cited
JPH07302848A
Cited
JPH08153808A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |