US6207978B1
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Flash memory cells having a modulation doped heterojunction structure
Assignee: Monterey Research LLC
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Filing: 2000-03-01
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Granted: 2001-03-27
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Expires: 2020-03-01
Abstract
Abstract A flash memory device and a method to manufacture the flash memory device. The flash memory device includes a modulation-doped heterostructure formed in a semiconductor substrate, a layer of tunnel oxide, a floating gate, a layer of dielectric, a control gate and source and drain regions formed in the substrate.
Inventors
- 👤 Richard Fastow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:28
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/01; H10D30/021; H10D30/0411; H10D30/751; H10D30/791; H10D30/798
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
87 words
A flash memory device comprising: a modulation-doped heterostructure in a semiconductor substrate, wherein the modulation-doped heterostructure comprises a layer of silicon that acts as a quantum well that becomes an electron channel under positive bias; a layer of tunnel oxide on a surface of the semiconductor substrate over the heterostructure; a floating gate on the layer of tunnel oxide; a layer of dielectric on the floating gate; a control gate on the layer of dielectric; and a source region and a drain region in the semiconductor substrate.
Claim 2
Dependent Claim
87 words
A flash memory device comprising: a modulation-doped heterostructure in a semiconductor substrate, wherein the modulation-doped heterostructure comprises a layer of silicon that acts as a quantum well that becomes an electron channel under positive bias; a layer of tunnel oxide on a surface of the semiconductor substrate over the heterostructure; a floating gate on the layer of tunnel oxide; a layer of dielectric on the floating gate; a control gate on the layer of dielectric; and a source region and a drain region in the semiconductor substrate.
Claim 3
Dependent Claim
28 words
The flash memory device of claim 1 wherein the modulation-doped heterostructure further comprises a layer of silicon germanium and a silicon cap layer on the layer of silicon.
Claim 4
Dependent Claim
56 words
The flash memory device of claim 2 wherein the modulation-doped heterostructure further comprises: an n-dpoed layer of silicon germanium; a p-doped layer of silicon germanium; a spacer layer between the n-doped lkayer of silicon germanium and the p-doped layer of silicon germanium; and a set back layer between the n-doped layer and the layer of silicon.
Claim 5
Dependent Claim
17 words
The flash memory device of claim 3 wherein the spacer layer is a layer of silicon germanium.
Claim 6
Dependent Claim
38 words
The flash memory device of claim 4 wherein the layer of silicon germanium on the layer of silicon has a concentration of Si x4 Ge y4 where x 4 and y 4 are fractions between 0 and 1.
Claim 7
Dependent Claim
24 words
The flash memory device of claim 5 wherein x 4 and y 4 satisfy the following conditions: 0.3≦x 4 ≦0.7; and 0.5≦y 4 ≦0.7.
Claim 8
Dependent Claim
34 words
The flash memory device of claim 6 wherein the n-doped layer of silicon germanium has a concentration of Si x3 Ge y3 wherein x 3 and y 3 are fractions between 0 and 1.
Claim 9
Dependent Claim
26 words
The flash memory device of claim 7 wherein x 3 and y 3 satisfy the following conditions: x 3 =approximately 0.7; and y 3 =approximately 0.3.
Claim 10
Dependent Claim
34 words
The flash memory device of claim 8 wherein the p-doped layer of silicon germanium has a concentration of Si x1 Ge y1 wherein x 1 and y 1 are fractions between 0 and 1.
Claim 11
Dependent Claim
26 words
The flash memory device of claim 9 wherein x 1 and y 1 satisfy the following conditions: x 1 =approximately 0.7; and y 1 =approximately 0.3.
Claim 12
Dependent Claim
34 words
The flash memory device of claim 10 wherein the spacer layer of silicon germanium has a concentration of Si x2 Ge y2 wherein x 2 and y 2 are fractions between 0 and 1.
Claim 13
Dependent Claim
26 words
The flash memory device of claim 11 wherein x 2 and y 2 satisfy the following conditions: x 2 =approximately 0.7; and y 2 =approximately 0.3.
References Cited (Backward Citations)
US6023079A
Cited
US5814854A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-26 | 2004-09-25 | 2005-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-26 | 2008-09-25 | 2009-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-26 | 2012-09-25 | 2013-03-27 | $7700.00 | Window Closed / Lapsed |