Compound semiconductor memory with floating gate

Claim 2

A compound semiconductor memory comprising: a substrate; a first semiconductor layer formed on said substrate, a channel being formed by said first semiconductor layer; a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer; a third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer; a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer; a gate electrode, formed on said fourth semiconductor layer, for controlling a conductivity of said channel; a source electrode electrically connected to said channel; and a drain electrode electrically connected to said channel, said gate electrode being located between said source electrode and said drain electrode; wherein said first semiconductor layer is formed of GaAs, said second semiconductor layer is formed of Al 0 .25 Ga 0 .75 As, said third semiconductor layer is formed of In 0 .25 Ga 0 .75 As and said fourth semiconductor layer is formed of Al 0 .5 Ga 0 .5 As.

Claim 3

The compound semiconductor memory according to claim 1, further comprising a buffer layer formed between said substrate and said first semiconductor layer.

Claim 4

The compound semiconductor memory according to claim 1, wherein said first semiconductor layer has an impurity density of approximately 1×10 10 to 1×10 17 cm -3 .

Claim 5

The compound semiconductor memory according to claim 1, further comprising a p type fifth semiconductor layer formed between said substrate and said first semiconductor layer, and a first control gate electrically connected to said fifth semiconductor layer.

Claim 6

The compound semiconductor memory according to claim 4, further comprising n type sixth and seventh semiconductor layers respectively formed between said source electrode and said first semiconductor layer, and between said drain electrode and said first semiconductor layer.

Claim 7

The compound semiconductor memory according to claim 1, further comprising: a fifth semiconductor layer formed between said third semiconductor layer and said fourth semiconductor layer and having a smaller electron affinity than that of said second semiconductor layer; a sixth semiconductor layer formed between said fifth semiconductor layer and said fourth semiconductor layer and having a greater electron affinity than those of said fifth semiconductor layer and said fourth semiconductor layer; and a changing mechanism which changes a potential of said sixth semiconductor layer.

Claim 8

A compound semiconductor memory comprising: a substrate; a first semiconductor layer formed on said substrate, a channel being formed by said first semiconductor layer; a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer, said second semiconductor layer having an electron affinity that is substantially constant in a thickness direction of said second semiconductor layer; a third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer; a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer; a gate electrode, formed on said fourth semiconductor layer, for controlling a conductivity of said channel; a source electrode electrically connected to said channel; and a drain electrode electrically connected to said channel, said gate electrode being located between said source electrode and said drain electrode; wherein said first semiconductor layer is of an n type, and said second and fourth semiconductor layers have impurity densities of approximately 1×10 10 to 1×10 17 cm -3 .

Claim 9

A compound semiconductor memory comprising: a substrate; a first semiconductor layer formed on said substrate, a channel being formed by said first semiconductor layer; a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer, said second semiconductor layer having an electron affinity that is substantially constant in a thickness direction of said second semiconductor layer; a third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer; a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer; a gate electrode, formed on said fourth semiconductor layer, for controlling a conductivity of said channel; a source electrode electrically connected to said channel; and a drain electrode electrically connected to said channel, said gate electrode being located between said source electrode and said drain electrode; wherein said first semiconductor layer is of an n type, and said second and fourth semiconductor layers have impurity densities of approximately 1×10 10 to 1×10 17 cm -3 .

Claim 10

The compound semiconductor memory according to claim 7, wherein said first semiconductor layer has an impurity density of approximately 1×10 10 to 1×10 17 cm -3 .

Claim 11

The compound semiconductor memory according to claim 7, further comprising a buffer layer formed between said substrate and said first semiconductor layer.

Claim 12

A compound semiconductor memory comprising: a substrate; a first semiconductor layer formed on said substrate, a channel being formed by said first semiconductor layer; a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer; a third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer; a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer; a gate electrode, formed on said fourth semiconductor layer, for controlling a conductivity of said channel; a source electrode electrically connected to said channel; and a drain electrode electrically connected to said channel, said gate electrode being located between said source electrode and said drain electrode; wherein said second semiconductor layer has an impurity density of approximately 1×10 17 to 1×10 20 cm -3 , and said fourth semiconductor layer has an impurity density of approximately 1×10 10 to 1×10 17 cm -3 .

Claim 13

A compound semiconductor memory comprising: a substrate; a first semiconductor layer formed on said substrate, a channel being formed by said first semiconductor layer; a second semiconductor layer deposited on said first semiconductor layer and having a smaller electron affinity than said first semiconductor layer; a third semiconductor layer deposited on said second semiconductor layer and having a greater electron affinity than said second semiconductor layer; a fourth semiconductor layer deposited on said third semiconductor layer and having a smaller electron affinity than said second semiconductor layer; a gate electrode, formed on said fourth semiconductor layer, for controlling a conductivity of said channel; a source electrode electrically connected to said channel; and a drain electrode electrically connected to said channel, said gate electrode being located between said source electrode and said drain electrode; wherein said second semiconductor layer has an impurity density of approximately 1×10 17 to 1×10 20 cm -3 , and said fourth semiconductor layer has an impurity density of approximately 1×10 10 to 1×10 17 cm -3 .

Claim 14

The compound semiconductor memory according to claim 10, further comprising a buffer layer formed between said substrate and said first semiconductor layer.

Claim 15

The compound semiconductor memory according to claim 10, wherein said first semiconductor layer has an impurity density of approximately 1×10 10 to 1×10 17 cm -3 .

Claim 16

A compound semiconductor memory comprising: a gate electrode for controlling a conductivity of a channel; and a floating gate formed between said gate electrode and said channel, said floating gate including a compound semiconductor layer having a high impurity density, a difference between electron affinities of said compound semiconductor layer and a first layer adjacent to said floating gate being higher than a difference between electron affinities of said compound semiconductor layer and a second layer adjacent to said floating gate, wherein said first layer is adjacent to said compound semiconductor layer and is disposed between said compound semiconductor layer and said gate electrode, and wherein said second layer is disposed adjacent to said compound semiconductor layer and is disposed between said compound semiconductor layer and said channel wherein an electron affinity of said second layer is substantially constant in a layer thickness direction of the second layer.

Claim 17

A compound semiconductor memory comprising: a gate electrode for controlling a conductivity of a channel; and a floating gate formed between said gate electrode and said channel, said floating gate including a compound semiconductor layer having a high impurity density, a difference between electron affinities of said compound semiconductor layer and a first layer adjacent to said floating gate being higher than a difference between electron affinities of said compound semiconductor layer and a second layer adjacent to said floating gate, wherein said first layer is adjacent to said compound semiconductor layer and is disposed between said compound semiconductor layer and said gate electrode, and wherein said second layer is disposed adjacent to said compound semiconductor layer and is disposed between said compound semiconductor layer and said channel wherein an electron affinity of said second layer is substantially constant in a layer thickness direction of the second layer.

Claim 18

The compound semiconductor memory of claim 13, wherein said first layer adjacent to the compound semiconductor layer has an impurity concentration of 1×10 17 to 1×10 20 cm -3 and the second layer adjacent to the compound semiconductor layer has an impurity concentration of 1×10 10 to 1×10 17 cm -3 .

Claim 19

A compound semiconductor memory comprising: a gate electrode for controlling a conductivity of a channel; and a floating gate formed between said gate electrode and said channel, wherein said floating gate includes a compound semiconductor layer having a high impurity density, and wherein said floating gate is formed so that it has a higher potential barrier on a side nearest to said gate electrode than on a side nearest to said channel.

Claim 20

A compound semiconductor memory comprising: a gate electrode for controlling a conductivity of a channel; and a floating gate formed between said gate electrode and said channel, wherein said floating gate includes a compound semiconductor layer having a high impurity density, and wherein said floating gate is formed so that it has a higher potential barrier on a side nearest to said gate electrode than on a side nearest to said channel.