US5814854A
Expired / Lapsed
US
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Highly scalable FLASH EEPROM cell
Assignee: Individual
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Filing: 1996-09-09
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Granted: 1998-09-29
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Expires: 2016-09-09
Abstract
Abstract The present invention is directed toward a novel type of FLASH EEPROM cell that is highly scalable in size, easy to fabricate, reliable and capable of in-system programmability. The semiconductor memory cell comprises a lightly doped n- region including a channel region, a first insulating layer overlying portions of said n- region, and a floating gate overlying said first insulating layer. The cell further includes a second insulating layer overlying said floating gate and a control gate overlying second insulating layer.
Inventors
- 👤 David K. Y. Liu
- 👤 Wenchi Ting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:04
CPC Classifications
H; H10; H10B; H10B69/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
57 words
A semiconductor memory cell comprising: a continuous n-channel region including a channel region; a first insulating layer overlying said continuous n-channel region wherein a neutral state of the n-channel region is active; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying said second insulating layer.
Claim 2
Dependent Claim
57 words
A semiconductor memory cell comprising: a continuous n-channel region including a channel region; a first insulating layer overlying said continuous n-channel region wherein a neutral state of the n-channel region is active; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying said second insulating layer.
Claim 3
Dependent Claim
41 words
The cell in claim 1 wherein the continuous n- region is confined and has a dose in the range of 1×10 12 cm-2 to 1×10 14 cm-2 such that the gate potential can fully modulate the conductivity of the n- region.
Claim 4
Dependent Claim
14 words
The cell in claim 1 further comprising a p-type well inside an n-type well.
Claim 5
Dependent Claim
13 words
The cell of claim 1 further comprising a p-type well inside a p-substrate.
Claim 6
Dependent Claim
16 words
The cell of claim 1 wherein the continuous n-channel region is implemented with a shallow n-implant.
Claim 7
Dependent Claim
15 words
The cell of claim 5 wherein the continuous n-region is further implemented with antimony implant.
Claim 8
Dependent Claim
26 words
The cell of claim 1 wherein the continuous n-channel region is implemented with semiconductor material with different bandgap to obtain a heterojunction structure with quantum well.
Claim 9
Dependent Claim
22 words
The cell of claim 1 wherein the continuous n-channel region is in the range of 500 Angstroms to 1500 Angstroms in thickness.
Claim 10
Dependent Claim
24 words
The cell of claim 1 further comprises an additional p-type high energy implant to further limit the continuous n-channel region to shallow junction depth.
Claim 11
Dependent Claim
22 words
The cell of claim 1 further comprises providing salicidation to the continuous n-channel region not underlying the gate to reduce series resistance.
Claim 12
Dependent Claim
27 words
The cell of claim 1 further comprises providing additional n-type implant to said continuous n-channel region not underlying the gate to further reduce source and drain resistance.
Claim 13
Dependent Claim
16 words
The cell of claim 1 wherein the continuous n-channel region overlying an insulator for SOI implementation.
Claim 14
Independent Claim
65 words
A method of programming a Flash memory cell having a continuous n- region, said method comprising the steps of: applying a first bias voltage to a control gate of said cell; biasing unselected wordlines at a second bias voltage; biasing unselected bitlines at a third bias voltage; and biasing a selected bitline at a ground potential, wherein a neutral state of the n-channel is active.
Claim 15
Independent Claim
65 words
A method of programming a Flash memory cell having a continuous n- region, said method comprising the steps of: applying a first bias voltage to a control gate of said cell; biasing unselected wordlines at a second bias voltage; biasing unselected bitlines at a third bias voltage; and biasing a selected bitline at a ground potential, wherein a neutral state of the n-channel is active.
Claim 16
Independent Claim
64 words
A method of erasing a Flash memory cell having a continuous n-channel region, comprising the steps of: applying a first positive bias voltage to P-well or P-substrate of said cell; and applying a second bias voltage to a control gate of said cell wherein the second bias voltage is 0 V or negative voltage, wherein a neutral state of the n-channel region is active.
Claim 17
Independent Claim
64 words
A method of erasing a Flash memory cell having a continuous n-channel region, comprising the steps of: applying a first positive bias voltage to P-well or P-substrate of said cell; and applying a second bias voltage to a control gate of said cell wherein the second bias voltage is 0 V or negative voltage, wherein a neutral state of the n-channel region is active.
Claim 18
Independent Claim
96 words
A method of reading/sensing a FLASH memory cell having a continuous n-channel region, comprising the steps of: biasing unselected wordlines at a first bias voltage; biasing a selected wordline at a ground potential; biasing unselected bitlines at a ground potential; applying a second bias voltage to a bitline of selected said cell; reading (sensing) the cell current from the bitline of the selected said cell; wherein from the said cell current the stored logic state on the floating gate of the said cell may be determined, wherein a neutral state of the n-channel region is active.
Claim 19
Independent Claim
96 words
A method of reading/sensing a FLASH memory cell having a continuous n-channel region, comprising the steps of: biasing unselected wordlines at a first bias voltage; biasing a selected wordline at a ground potential; biasing unselected bitlines at a ground potential; applying a second bias voltage to a bitline of selected said cell; reading (sensing) the cell current from the bitline of the selected said cell; wherein from the said cell current the stored logic state on the floating gate of the said cell may be determined, wherein a neutral state of the n-channel region is active.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-28 | 2002-03-30 | 2002-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-28 | 2006-03-30 | 2006-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-28 | 2010-03-30 | 2010-09-29 | $7700.00 | Window Closed / Lapsed |