US5991200A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory device
Assignee: Renesas Electronics Corp
•
Filing: 1995-06-06
•
Granted: 1999-11-23
•
Expires: 2015-06-06
Abstract
Abstract Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.
Inventors
- 👤 Koichi Seki
- 👤 Takeshi Wada
- 👤 Tadashi Muto
- 👤 Kazuyoshi Shoji
- 👤 Yasurou Kubota
- 👤 Hitoshi Kume
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:10
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/10; G11C16/12; G11C16/14; G11C16/16; G11C16/30; G11C16/32; G11C2216/00; G11C2216/12; G11C2216/20
Claims Analysis
Total Claims: 54
Claim 1
Independent Claim
109 words
A semiconductor nonvolatile memory device, formed on a semiconductor chip, in which external address signals are supplied from first external terminals, comprising: a plurality of nonvolatile memory cells; and a circuit formed on the same semiconductor chip as said memory cells including a verify address generating circuit for sequentially generating verify address signals which indicate predetermined ones of said plurality of nonvolatile memory cells, and an erasing control circuit responsive to an external instruction supplied from second external terminals of the device for executing an erase operation and an erase verifying operation for the nonvolatile memory cells indicated by the verify address signals to guarantee an adequate erase margin.
Claim 2
Dependent Claim
109 words
A semiconductor nonvolatile memory device, formed on a semiconductor chip, in which external address signals are supplied from first external terminals, comprising: a plurality of nonvolatile memory cells; and a circuit formed on the same semiconductor chip as said memory cells including a verify address generating circuit for sequentially generating verify address signals which indicate predetermined ones of said plurality of nonvolatile memory cells, and an erasing control circuit responsive to an external instruction supplied from second external terminals of the device for executing an erase operation and an erase verifying operation for the nonvolatile memory cells indicated by the verify address signals to guarantee an adequate erase margin.
Claim 3
Dependent Claim
102 words
A semiconductor nonvolatile memory device according to claim 1, wherein said circuit further comprises: a pre-write address generating circuit for sequentially generating pre-write address signals for indicating predetermined ones of said plurality of nonvolatile memory cells; and a pre-write circuit responsive to said external instruction for executing a write operation which changes a threshold voltage of nonvolatile memory cells indicated by said pre-write address signals into a first threshold region from a second threshold region so that the threshold voltage in each of the nonvolatile memory cells to be erased is placed in said first threshold region before executing the erase operation.
Claim 4
Dependent Claim
75 words
A semiconductor nonvolatile memory device according to claim 1, wherein said circuit further comprises: a pre-write circuit responsive to said external instruction for executing a write operation which changes a threshold voltage of said nonvolatile memory cells into a first threshold region from a second threshold region so that the respective threshold voltages of said plurality of nonvolatile memory cells to be erased are placed in said first threshold region before executing the erase operation.
Claim 5
Dependent Claim
102 words
A semiconductor nonvolatile memory device according to claim 1, wherein said circuit further comprises: a pre-write address generating circuit for sequentially generating pre-write address signals for indicating predetermined ones of said plurality of nonvolatile memory cells; and a pre-write circuit responsive to said external instruction for executing a write operation which changes a threshold voltage of nonvolatile memory cells indicated by said pre-write address signals into a first threshold region from a second threshold region so that the threshold voltage in each of the nonvolatile memory cells to be erased is placed in said first threshold region before executing the erase operation.
Claim 6
Dependent Claim
53 words
A semiconductor nonvolatile memory device according to claim 1, wherein the verify address generating circuit and the erasing control circuit automatically execute the verifying operation for memory cells specified by the verify address signals following an erasing operation without requiring address signals from an external microprocessor to which the memory device is coupled.
Claim 7
Dependent Claim
91 words
A semiconductor nonvolatile memory device according to claim 1, wherein the external instruction for executing the erase operation and the erase verifying operation is provided from an external processing unit which is separate from the semiconductor chip on which the semiconductor nonvolatile memory device is formed, and wherein the erase operation and the erase verifying operation are carried out automatically in response to the external instruction using the verify address signals generated by the verify address generating circuit on the semiconductor chip, thereby reducing the load on the external processing unit.
Claim 8
Dependent Claim
231 words
A semiconductor nonvolatile memory device formed on a semiconductor chip, comprising: a plurality of memory cells in each of which a threshold voltage is changed into a first threshold voltage from a second threshold region by an erase operation; external address terminals for receiving external address signals for indicating predetermined ones of said plurality of memory cells to be accessed from outside of said semiconductor nonvolatile memory device; and a circuit formed on the same semiconductor substrate as said memory cells including: a verify address generating circuit for generating verify address signals for indicating predetermined ones of said plurality of memory cells; and an erase control circuit responsive to an external instruction applied from outside the semiconductor nonvolatile memory device for executing an erase verifying operation after executing the erase operation for memory cells, said erase verifying operation including a first operation for verifying whether or not the threshold voltages of the memory cells indicated by the verify address signals have been changed into the first threshold region, a second operation for repeating execution of the erase operation if the change into the first threshold region is not verified in the first operation, and a third operation for replacing the verify address signals generated earlier with different address signals newly generated by the verify address generating circuit if the change into the first threshold region is verified in the first operation.
Claim 9
Dependent Claim
231 words
A semiconductor nonvolatile memory device formed on a semiconductor chip, comprising: a plurality of memory cells in each of which a threshold voltage is changed into a first threshold voltage from a second threshold region by an erase operation; external address terminals for receiving external address signals for indicating predetermined ones of said plurality of memory cells to be accessed from outside of said semiconductor nonvolatile memory device; and a circuit formed on the same semiconductor substrate as said memory cells including: a verify address generating circuit for generating verify address signals for indicating predetermined ones of said plurality of memory cells; and an erase control circuit responsive to an external instruction applied from outside the semiconductor nonvolatile memory device for executing an erase verifying operation after executing the erase operation for memory cells, said erase verifying operation including a first operation for verifying whether or not the threshold voltages of the memory cells indicated by the verify address signals have been changed into the first threshold region, a second operation for repeating execution of the erase operation if the change into the first threshold region is not verified in the first operation, and a third operation for replacing the verify address signals generated earlier with different address signals newly generated by the verify address generating circuit if the change into the first threshold region is verified in the first operation.
Claim 10
Dependent Claim
53 words
A semiconductor nonvolatile memory device according to claim 7, wherein the verify address generating circuit and the erasing control circuit automatically execute the verifying operation for memory cells specified by the verify address signals following an erasing operation without requiring address signals from an external microprocessor to which the memory device is coupled.
Claim 11
Dependent Claim
91 words
A semiconductor nonvolatile memory device according to claim 7, wherein the external instruction for executing the erase operation and the erase verifying operation is provided from an external processing unit which is separate from the semiconductor chip on which the semiconductor nonvolatile memory device is formed, and wherein the erase operation and the erase verifying operation are carried out automatically in response to the external instruction using the verify address signals generated by the verify address generating circuit on the semiconductor chip, thereby reducing the load on the external processing unit.
Claim 12
Dependent Claim
26 words
A semiconductor nonvolatile memory device according to claim 7, wherein the first operation is repeated after executing one of the second operation and the third operation.
Claim 13
Dependent Claim
21 words
A semiconductor nonvolatile memory device according to claim 10, further comprising external terminals for receiving signals for representing said external instruction.
Claim 14
Dependent Claim
71 words
A semiconductor nonvolatile memory device according to claim 7, further comprising: a pre-write circuit responsive to said external instruction for executing a write operation which changes the threshold voltage of the nonvolatile memory cells into said second threshold region from said first threshold region, so that the respective threshold voltages of said plurality of memory cells to be erased are placed in said second threshold region before performing the erase operation.
Claim 15
Dependent Claim
26 words
A semiconductor nonvolatile memory device according to claim 12, wherein the first operation is repeated after executing one of the second operation and the third operation.
Claim 16
Dependent Claim
67 words
A semiconductor nonvolatile memory device according to claim 13, wherein said second threshold region corresponds to a predetermined voltage potential region and said first threshold region corresponds to a lower voltage potential region than said predetermined voltage potential region, and wherein each of said plurality of memory cells includes an N-channel type transistor having a drain region, a source region, a floating gate and a control gate.
Claim 17
Dependent Claim
21 words
A semiconductor nonvolatile memory device according to claim 14, further comprising external terminals for receiving signals for representing said external instruction.
Claim 18
Dependent Claim
97 words
A semiconductor nonvolatile memory device according to claim 7, further comprising: a pre-write address generating circuit for sequentially generating pre-write address signals for indicating predetermined ones of said plurality of memory cells; and a pre-write circuit responsive to said external instruction for executing a write operation which changes the threshold voltage of nonvolatile memory cells indicated by said pre-write address signals into said second threshold region from said first threshold region, so that the threshold voltage in each of the memory cells to be erased is placed in said second threshold region before executing the erase operation.
Claim 19
Dependent Claim
26 words
A semiconductor nonvolatile memory device according to claim 16, wherein the first operation is repeated after executing one of the second operation and the third operation.
Claim 20
Dependent Claim
67 words
A semiconductor nonvolatile memory device according to claim 17, wherein said second threshold region corresponds to a predetermined voltage potential region and said first threshold region corresponds to a lower voltage potential region than said predetermined voltage potential region, and wherein each of said plurality of memory cells includes an N-channel type transistor having a drain region, a source region, a floating gate and a control gate.
Claim 21
Dependent Claim
21 words
A semiconductor nonvolatile memory device according to claim 18, further comprising external terminals for receiving signals for representing said external instruction.
Claim 22
Dependent Claim
243 words
A single chip semiconductor nonvolatile memory device having a plurality of operation modes, comprising: a plurality of memory cells; external terminals for receiving external address signals in a read operation mode for reading out stored data in a memory cell designated by the external address signals; an output circuit outputting stored data in a memory cell indicated by the external address signals, in the read operation mode; and erase control circuit which includes an address generating circuit sequentially generating address signals, and which executes an erase operation for changing a threshold voltage into a predetermined threshold voltage region for predetermined ones of the plurality of memory cells and an erase verify operation thereafter in an erase operation mode for changing threshold voltage of said predetermined ones of the plurality of memory cells into the predetermined threshold voltage region, wherein the erase verify operation includes a verify operation for verifying whether a threshold voltage of a memory cell designated by address signals generated by the address generating circuit is in the predetermined threshold voltage region, and the erase operation which is executed if change of the threshold voltage of the designated memory cell into the predetermined threshold voltage region is not verified, and wherein another erase verify operation is executed for a different memory cell designated by different address signals generated by the address generating circuit if change of the threshold voltage of the memory cell into the predetermined threshold voltage region is verified.
Claim 23
Dependent Claim
243 words
A single chip semiconductor nonvolatile memory device having a plurality of operation modes, comprising: a plurality of memory cells; external terminals for receiving external address signals in a read operation mode for reading out stored data in a memory cell designated by the external address signals; an output circuit outputting stored data in a memory cell indicated by the external address signals, in the read operation mode; and erase control circuit which includes an address generating circuit sequentially generating address signals, and which executes an erase operation for changing a threshold voltage into a predetermined threshold voltage region for predetermined ones of the plurality of memory cells and an erase verify operation thereafter in an erase operation mode for changing threshold voltage of said predetermined ones of the plurality of memory cells into the predetermined threshold voltage region, wherein the erase verify operation includes a verify operation for verifying whether a threshold voltage of a memory cell designated by address signals generated by the address generating circuit is in the predetermined threshold voltage region, and the erase operation which is executed if change of the threshold voltage of the designated memory cell into the predetermined threshold voltage region is not verified, and wherein another erase verify operation is executed for a different memory cell designated by different address signals generated by the address generating circuit if change of the threshold voltage of the memory cell into the predetermined threshold voltage region is verified.
Claim 24
Dependent Claim
19 words
A single chip semiconductor nonvolatile memory device according to claim 20, wherein the external terminals are external address terminals.
Claim 25
Dependent Claim
64 words
A single-chip semiconductor nonvolatile memory device according to claim 20, wherein the erase operation and the erase verifying operation are carried out automatically, using the address signals generated by the address generating circuit, in response to an external instruction provided by an external processing unit which is separate from the single-chip semiconductor nonvolatile memory device, thereby reducing the load on the external processing unit.
Claim 26
Dependent Claim
20 words
A single chip semiconductor nonvolatile memory device according to claim 20, wherein the address generating circuit includes an address counter.
Claim 27
Dependent Claim
43 words
A single chip semiconductor nonvolatile memory device according to claim 23, wherein each of the memory cells includes a single memory transistor in which a threshold voltage is changed into the predetermined threshold voltage region in response to supplying a predetermined voltage thereto.
Claim 28
Dependent Claim
278 words
A single chip semiconductor nonvolatile memory device having a plurality of operation modes, comprising: a plurality of memory cells in each of which a threshold voltage thereof is changed into a predetermined threshold voltage region in response to supplying a predetermined voltage potential thereto; external terminals for receiving external address signals in a read operation mode for reading out data stored in a memory cell in accordance with the received external address signals; an output circuit outputting data stored in a memory cell designated by the external address signals from the external address terminal, in the read operation mode; an erase voltage providing circuit which supplies the predetermined voltage potential to predetermined ones of the plurality of memory cells in an erase operation mode for changing a threshold voltage of each of said Predetermined ones of the plurality of memory cells into the predetermined threshold voltage region; an address counter sequentially generating address signals; a detecting circuit which detects whether a threshold voltage of a memory cell indicated by address signals generated from the address counter is changed into the predetermined threshold voltage region; and a control circuit which operates the erase voltage providing circuit and the detecting circuit thereafter, if the detecting circuit indicates that the threshold voltage of the memory cell designated by the address signals from the address counter is out the predetermined threshold voltage region, and which replaces the address signal with different address signals generated by the address counter and operates the detecting circuit, if the detecting circuit indicates that the threshold voltage of the memory cell designated by the address signals from the address counter is in the predetermined threshold voltage region.
Claim 29
Dependent Claim
278 words
A single chip semiconductor nonvolatile memory device having a plurality of operation modes, comprising: a plurality of memory cells in each of which a threshold voltage thereof is changed into a predetermined threshold voltage region in response to supplying a predetermined voltage potential thereto; external terminals for receiving external address signals in a read operation mode for reading out data stored in a memory cell in accordance with the received external address signals; an output circuit outputting data stored in a memory cell designated by the external address signals from the external address terminal, in the read operation mode; an erase voltage providing circuit which supplies the predetermined voltage potential to predetermined ones of the plurality of memory cells in an erase operation mode for changing a threshold voltage of each of said Predetermined ones of the plurality of memory cells into the predetermined threshold voltage region; an address counter sequentially generating address signals; a detecting circuit which detects whether a threshold voltage of a memory cell indicated by address signals generated from the address counter is changed into the predetermined threshold voltage region; and a control circuit which operates the erase voltage providing circuit and the detecting circuit thereafter, if the detecting circuit indicates that the threshold voltage of the memory cell designated by the address signals from the address counter is out the predetermined threshold voltage region, and which replaces the address signal with different address signals generated by the address counter and operates the detecting circuit, if the detecting circuit indicates that the threshold voltage of the memory cell designated by the address signals from the address counter is in the predetermined threshold voltage region.
Claim 30
Dependent Claim
96 words
A single chip semiconductor nonvolatile memory device according to claim 25, wherein the plurality of memory cells are coupled to a plurality of word lines from which a word line is indicated in according to the external address signals and the indicated word line is supplied with a read voltage in the read operation mode, and wherein the detecting circuit includes a verify voltage providing circuit which generates a verify voltage being different from the read voltage and which provides the verify voltage to a word line designated by address signals generated from the address counter.
Claim 31
Dependent Claim
19 words
A single chip semiconductor nonvolatile memory device according to claim 25, wherein the external terminals are external address terminals.
Claim 32
Dependent Claim
63 words
A single-chip semiconductor nonvolatile memory device according to claim 25, wherein the erase operation and the erase verifying operation are carried out automatically, using the address signals generated by the address counter, in response to an external instruction provided by an external processing unit which is separate from the single-chip semiconductor nonvolatile memory device, thereby reducing the load on the external processing unit.
Claim 33
Dependent Claim
246 words
A single chip semiconductor nonvolatile memory device having a plurality of operation modes, comprising: a plurality of memory cells; external terminals for receiving external address signals in a read operation mode in which stored data in memory cells designated by the external address signals are read out; a data output circuit outputting stored data in memory cells designated by the external address signals in the read operation mode; an erase control circuit which includes an address counter sequentially generating address signals, and which executes an erase operation for changing a threshold voltage of each of the memory cells into a predetermined threshold region and a verify operation for verifying whether a threshold voltage of each of memory cells designated by address signals generated from the address counter has been changed into the predetermined threshold voltage by executing the erase operation, in an erase operation mode that changes the threshold voltage of each of the plurality of memory cells into the predetermined threshold region, wherein if the threshold voltage of each of the memory cells designated by the address signals from the address counter is changed into the predetermined threshold voltage region, the verify operation for different memory cells designated by different address signals generated by the address counter is executed, and wherein if a memory cell having a threshold voltage out the predetermined threshold voltage region is included in the memory cells designated by the address signals from the address counter, the erase operation is executed.
Claim 34
Dependent Claim
246 words
A single chip semiconductor nonvolatile memory device having a plurality of operation modes, comprising: a plurality of memory cells; external terminals for receiving external address signals in a read operation mode in which stored data in memory cells designated by the external address signals are read out; a data output circuit outputting stored data in memory cells designated by the external address signals in the read operation mode; an erase control circuit which includes an address counter sequentially generating address signals, and which executes an erase operation for changing a threshold voltage of each of the memory cells into a predetermined threshold region and a verify operation for verifying whether a threshold voltage of each of memory cells designated by address signals generated from the address counter has been changed into the predetermined threshold voltage by executing the erase operation, in an erase operation mode that changes the threshold voltage of each of the plurality of memory cells into the predetermined threshold region, wherein if the threshold voltage of each of the memory cells designated by the address signals from the address counter is changed into the predetermined threshold voltage region, the verify operation for different memory cells designated by different address signals generated by the address counter is executed, and wherein if a memory cell having a threshold voltage out the predetermined threshold voltage region is included in the memory cells designated by the address signals from the address counter, the erase operation is executed.
Claim 35
Dependent Claim
19 words
A single chip semiconductor nonvolatile memory device according to claim 29, wherein the external terminals are external address terminals.
Claim 36
Dependent Claim
63 words
A single-chip semiconductor nonvolatile memory device according to claim 29, wherein the erase operation and the erase verifying operation are carried out automatically, using the address signals generated by the address counter, in response to an external instruction provided by an external processing unit which is separate from the single-chip semiconductor nonvolatile memory device, thereby reducing the load on the external processing unit.
Claim 37
Dependent Claim
43 words
A single chip semiconductor nonvolatile memory device according to claim 29, wherein each of the memory cells includes a single memory transistor in which a threshold voltage is changed into the predetermined threshold voltage region in response to supplying a predetermined voltage thereto.
Claim 38
Dependent Claim
75 words
A single chip semiconductor nonvolatile memory device according to claim 32, further comprising a plurality of word lines each of which is coupled to memory cells, wherein one of the plurality of word lines is designated by ones of the external address signals in the read operation mode and wherein one of the plurality of word lines is designated by ones of the address signals generated by the address counter in the erase operation mode.
Claim 39
Dependent Claim
58 words
A single chip semiconductor nonvolatile memory device according to claim 33, wherein each of memory cells includes a single memory transistor having a control gate coupled to a word line, and wherein a threshold voltage of each of the memory cells is changed into the predetermined threshold voltage region in response to supplying of a predetermined voltage thereto.
Claim 40
Dependent Claim
269 words
A single chip semiconductor nonvolatile memory device having a plurality of operation modes, comprising: a plurality of memory cells in each of which a threshold voltage thereof is changed into a predetermined threshold voltage region in response to supplying a predetermined voltage potential thereto; external terminals for receiving external address signals in a read operation mode for reading out data stored in memory cells; an output circuit outputting data stored in memory cells designated by the external address signals from the external address terminals, in the read operation mode; an erase voltage providing circuit which supplies the predetermined voltage potential to the plurality of memory cells, in an erase operation mode for changing a threshold voltage of each of the plurality of memory cells into the predetermined threshold voltage region; an address counter sequentially generating address signals; a detecting circuit which detects whether a threshold voltage of each of memory cells indicated by address signals generated from the address counter is changed into the predetermined threshold voltage region; and a control circuit which operates the erase voltage providing circuit and the detecting circuit thereafter, if the detecting circuit indicates that a memory cell whose threshold voltage is out the predetermined threshold voltage region is included in the memory cells designated by the address signals from the address counter, and which replaces the address signals with different address signals generated by the address counter and operates the detecting circuit, if the detecting circuit indicates that the threshold voltage of each of the memory cells designated by the address signals from the address counter are in the predetermined threshold voltage region.
Claim 41
Dependent Claim
269 words
A single chip semiconductor nonvolatile memory device having a plurality of operation modes, comprising: a plurality of memory cells in each of which a threshold voltage thereof is changed into a predetermined threshold voltage region in response to supplying a predetermined voltage potential thereto; external terminals for receiving external address signals in a read operation mode for reading out data stored in memory cells; an output circuit outputting data stored in memory cells designated by the external address signals from the external address terminals, in the read operation mode; an erase voltage providing circuit which supplies the predetermined voltage potential to the plurality of memory cells, in an erase operation mode for changing a threshold voltage of each of the plurality of memory cells into the predetermined threshold voltage region; an address counter sequentially generating address signals; a detecting circuit which detects whether a threshold voltage of each of memory cells indicated by address signals generated from the address counter is changed into the predetermined threshold voltage region; and a control circuit which operates the erase voltage providing circuit and the detecting circuit thereafter, if the detecting circuit indicates that a memory cell whose threshold voltage is out the predetermined threshold voltage region is included in the memory cells designated by the address signals from the address counter, and which replaces the address signals with different address signals generated by the address counter and operates the detecting circuit, if the detecting circuit indicates that the threshold voltage of each of the memory cells designated by the address signals from the address counter are in the predetermined threshold voltage region.
Claim 42
Dependent Claim
19 words
A single chip semiconductor nonvolatile memory device according to claim 35, wherein the external terminals are external address terminals.
Claim 43
Dependent Claim
63 words
A single-chip semiconductor nonvolatile memory device according to claim 35, wherein the erase operation and the erase verifying operation are carried out automatically, using the address signals generated by the address counter, in response to an external instruction provided by an external processing unit which is separate from the single-chip semiconductor nonvolatile memory device, thereby reducing the load on the external processing unit.
Claim 44
Dependent Claim
96 words
A single chip semiconductor nonvolatile memory device according to claim 35, wherein the plurality of memory cells are coupled to a plurality of word lines from which a word line is designated in according to the external address signals and the designated word line is supplied with a read voltage in the read operation mode, and wherein the detecting circuit includes a verify voltage providing circuit which generates a verify voltage being different from the read voltage and which provides the verify voltage to a word line designated by address signals generated from the address counter.
Claim 45
Dependent Claim
61 words
A single chip semiconductor nonvolatile memory device according to claim 38, wherein a word line among the plurality of word lines is designated by decoding ones of the external address signals in the read operation mode, and by decoding the address signals generated by the address counter instead of the ones of the external address signals in the erase operation mode.
Claim 46
Dependent Claim
30 words
A single chip semiconductor nonvolatile memory device according to claim 39, wherein each of the memory cells includes a memory transistor having a control gate coupled to a word line.
Claim 47
Dependent Claim
150 words
A single chip semiconductor nonvolatile memory device comprising: a plurality of memory cells in each of which a threshold voltage is changed from a first threshold voltage region to a second voltage region by supplying a predetermined voltage thereto; an address counter sequentially generating address signals; and control circuitry which detects whether a threshold voltage of a memory cell designated by address signals from the address counter is in the second threshold voltage region, which supplies a memory cell with the predetermined voltage if the detection indicates that the threshold voltage of the memory cell designated by the address signals is out the second threshold voltage region, and which checks a threshold voltage of a different memory cell designated by different address signals from the address counter if the detection indicates that the threshold voltage of the memory cell designated by the address signals is in the second threshold voltage.
Claim 48
Dependent Claim
150 words
A single chip semiconductor nonvolatile memory device comprising: a plurality of memory cells in each of which a threshold voltage is changed from a first threshold voltage region to a second voltage region by supplying a predetermined voltage thereto; an address counter sequentially generating address signals; and control circuitry which detects whether a threshold voltage of a memory cell designated by address signals from the address counter is in the second threshold voltage region, which supplies a memory cell with the predetermined voltage if the detection indicates that the threshold voltage of the memory cell designated by the address signals is out the second threshold voltage region, and which checks a threshold voltage of a different memory cell designated by different address signals from the address counter if the detection indicates that the threshold voltage of the memory cell designated by the address signals is in the second threshold voltage.
Claim 49
Dependent Claim
42 words
A single chip semiconductor nonvolatile memory device according to claim 41, wherein the check of the threshold voltage of the different memory cell is to detect whether the threshold voltage of the different memory cell is in the second threshold voltage region.
Claim 50
Dependent Claim
63 words
A single-chip semiconductor nonvolatile memory device according to claim 41, wherein the erase operation and the erase verifying operation are carried out automatically, using the address signals generated by the address counter, in response to an external instruction provided by an external processing unit which is separate from the single-chip semiconductor nonvolatile memory device, thereby reducing the load on the external processing unit.
Claim 51
Dependent Claim
79 words
A semiconductor nonvolatile memory device formed on a single semiconductor chip, comprising: a plurality of memory cells in each of which a threshold voltage is changed from a first threshold voltage region to the second threshold voltage region in response to supplying of a predetermined voltage thereto; and a control circuit which detects whether the threshold voltage of each of the memory cells is in the second threshold voltage region after supplying the predetermined voltage to the memory cells.
Claim 52
Dependent Claim
79 words
A semiconductor nonvolatile memory device formed on a single semiconductor chip, comprising: a plurality of memory cells in each of which a threshold voltage is changed from a first threshold voltage region to the second threshold voltage region in response to supplying of a predetermined voltage thereto; and a control circuit which detects whether the threshold voltage of each of the memory cells is in the second threshold voltage region after supplying the predetermined voltage to the memory cells.
Claim 53
Dependent Claim
41 words
A semiconductor nonvolatile memory device according to claim 44, wherein the control circuit supplies the predetermined voltage to the memory cells again if the detection indicates the threshold voltage of the memory cells is out of the second threshold voltage region.
Claim 54
Dependent Claim
46 words
A semiconductor nonvolatile memory device according to claim 45, wherein the memory device further includes a verify address generating circuit formed on said single semiconductor chip for sequentially generating verify address signals to indicate which of said memory cells will be supplied with said predetermined voltage.
References Cited (Backward Citations)
US4460982A
Cited
US4698750A
Cited
US5155701A
Cited
US4811294A
Cited
JPS6245182A
Cited
JPS62119796A
Cited
US4742492A
Cited
US4805151A
Cited
JPS6417299A
Cited
US5034922A
Cited
JPH0210596A
Cited
US5053990A
Cited
US5222046A
Cited
US5602987A
Cited
US5077691A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-22 | 2003-05-24 | 2003-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-22 | 2007-05-24 | 2007-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-22 | 2011-05-24 | 2011-11-23 | $7700.00 | Window Closed / Lapsed |