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JPH0210596A Expired / Lapsed JP ⏱️ 0.0 years remaining

Method of erasing memory, method of programming memor and method of erasing and programming memory

Assignee: Intel Corp
•
Filing: 1989-02-17
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Granted: —
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Expires: 2009-02-17
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Abstract

Abstract PURPOSE: To program a flash memory device via a data port and to enable an erasing command port architecture by incorporating a circuit means into the same semiconductor chip as a memory executing erasing, programming and erasing/programing test in a circuit. CONSTITUTION: A program command is inputted into a condition resistor 35 and command resistor 37 in a first cycle of writing enable signals WE. An address latch 13 and data latch 22 are loaded in a second WE cycle. The first transition end of the second WE cycle is started to program by generating control signals to a program voltage generator 25 with a condition decoder 36. Next, a high voltage VPP is applied to a gate and drain of an addressed cell of a memory array 11 with the program voltage generator 25. Programming is finished by writing a program test command into the condition resistor 35 and the command resistor 37 in a third WE cycle, and an internal limit voltage is set in order to test a newly programed bit.

Inventors

  • 👤 Jerry A Kreifels
  • 👤 ジエリイ・エイ・クライフエルス
  • 👤 Alan Baker
  • 👤 アラン・ベーカー
  • 👤 George Hoekstra
  • 👤 ジヨージ・ヘクストラ
  • 👤 Virgil N Kynett
  • 👤 ヴアージル・ナイルス・キネツト
  • 👤 Steven Wells
  • 👤 ステイーヴン・ウエルズ
  • 👤 Mark Winston
  • 👤 マーク・ウインストン

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 21:00
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/10; G11C16/14; G11C16/16; G11C16/3454; G11C16/3459

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