Patent US6300649B1 successfully refreshed from Google Patents.
US6300649B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
Assignee: University of California, San Diego
•
Filing: 2000-08-04
•
Granted: 2001-10-09
•
Expires: 2020-08-04
Abstract
Abstract An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.
Inventors
- 👤 Chenming Hu
- 👤 Mansun John Chan
- 👤 Hsing-Jen Wann
- 👤 Ping Keung Ko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:16
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/01; H10D30/021; H10D30/0217; H10D30/031; H10D30/0321; H10D30/0323; H10D30/6704; H10D30/6708; H10D30/6711; H10D30/6713; H10D30/6715; H10D30/6717; H10D30/6757; H10D87/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
94 words
An integrated circuit comprising a first field effect transistor and a second field effect transistor formed in a semiconductor material layer on an insulting layer, each transistor having a source region, a drain region, and a channel region between said source region and said drain region, said channel region of said first field effect transistor being recessed in height below said source region and said drain region of said first field effect transistor, whereby said first field effect transistor and said second field effect transistor have different threshold voltages due to different channel thicknesses.
Claim 2
Dependent Claim
94 words
An integrated circuit comprising a first field effect transistor and a second field effect transistor formed in a semiconductor material layer on an insulting layer, each transistor having a source region, a drain region, and a channel region between said source region and said drain region, said channel region of said first field effect transistor being recessed in height below said source region and said drain region of said first field effect transistor, whereby said first field effect transistor and said second field effect transistor have different threshold voltages due to different channel thicknesses.
Claim 3
Dependent Claim
26 words
The integrated circuit as defined by claim 1 wherein said channel region of said first field effect transistor also has a dopant implant for threshold adjustment.
Claim 4
Dependent Claim
33 words
The integrated circuit as defined by claim 1 wherein said channel region of said second field effect transistor is recessed in height but less than the recess of the first field effect transistor.
Claim 5
Dependent Claim
31 words
The integrated circuit as defined in claim 3 wherein the channel regions of said first field effect transistor and said second field effect transistor also have dopant implants for threshold adjustment.
Claim 6
Dependent Claim
31 words
The integrated circuit as defined by claim 1 wherein the channel regions of said first field effect transistor and said second field effect transistor also have dopant implants for threshold adjustment.
Claim 7
Dependent Claim
120 words
An integrated circuit comprising a first field effect transistor formed in a semiconductor material layer on an insulating layer in a supporting semiconductor substrate, and a second field effect transistor formed in said semiconductor substrate adjacent to said first field effect transistor, said second field effect transistor forming an element in an electrostatic discharge protection circuit, each transistor having a source region, a drain region, and a channel region between said source region and said drain region, said channel region of said first field effect transistor being recessed in height below said source region and said drain region of said first field effect transistor, whereby said first field effect transistor and said second field effect transistor have different threshold voltages.
Claim 8
Dependent Claim
120 words
An integrated circuit comprising a first field effect transistor formed in a semiconductor material layer on an insulating layer in a supporting semiconductor substrate, and a second field effect transistor formed in said semiconductor substrate adjacent to said first field effect transistor, said second field effect transistor forming an element in an electrostatic discharge protection circuit, each transistor having a source region, a drain region, and a channel region between said source region and said drain region, said channel region of said first field effect transistor being recessed in height below said source region and said drain region of said first field effect transistor, whereby said first field effect transistor and said second field effect transistor have different threshold voltages.
Claim 9
Dependent Claim
33 words
The integrated circuit as defined by claim 6 wherein said channel region of said second field effect transistor is recessed in height but less than the recess of the first field effect transistor.
Claim 10
Dependent Claim
30 words
The integrated circuit as defined in claim 7 wherein the channel regions of said first field effect transistor and said second field effect transistor have dopant implants for threshold adjustment.
Claim 11
Dependent Claim
30 words
The integrated circuit as defined by claim 6 wherein the channel regions of said first field effect transistor and said second field effect transistor have dopant implants for threshold adjustment.
References Cited (Backward Citations)
US5294555A
Cited
US4954855A
Cited
US5293053A
Cited
US4746960A
Cited
US4889829A
Cited
US4985744A
Cited
US4899202A
Cited
US5164805A
Cited
US5125007A
Cited
US5116771A
Cited
US5264721A
Cited
US5160989A
Cited
US5212574A
Cited
US5072277A
Cited
US5095348A
Cited
US5047356A
Cited
US5159416A
Cited
US5212397A
Cited
US5102809A
Cited
US5187113A
Cited
US5185535A
Cited
EP0523800A1
Cited
US5258318A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-08 | 2005-04-09 | 2005-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-08 | 2009-04-09 | 2009-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-08 | 2013-04-09 | 2013-10-09 | $7700.00 | Window Closed / Lapsed |