Extended body contact for semiconductor over insulator transistor

Claim 2

A transistor, comprising: an insulating layer; a semiconductor mesa having a base adjacent said insulating layer and a top opposite said base, said semiconductor mesa comprising: a source region within said semiconductor mesa, said source region of a first conductivity type; a drain region within said semiconductor mesa, said drain region of said first conductivity type; a body region in contact with said insulating layer and extending to the top of said mesa and located between said source and drain regions, said body region of a second conductivity type and of a first dopant level; a first contact region of resistivity lower than that of said body region disposed along substantially the entire width of said body region and adjacent said source region and said body region, said first contact region in contact with said insulating layer and underlying at least a portion of said source region and extending substantially no farther toward said body region than the junction between said source region and said body region; a segment region between said source region and said insulating layer, and further contacting said first contact region; and a vertical contact region adjoining said segment region and extending toward said top of said semiconductor mesa.

Claim 3

The transistor of claim 1 wherein said vertical contact region is of said second conductivity type and of second dopant level greater in dopant concentration than said first dopant level.

Claim 4

The transistor of claim 1 wherein said segment region is of said second conductivity type and of a second dopant level greater in concentration than said first dopant level.

Claim 5

The transistor of claim 1 wherein said transistor is a lightly doped drain transistor.

Claim 6

A transistor, comprising: an insulating layer; a semiconductor mesa having a base adjacent said insulating layer, said semiconductor mesa comprising: a source region within said semiconductor mesa, said source region of a first conductivity type and having a dopant concentration equal to or greater than 10 20 /cm 3 ; a drain region within said semiconductor mesa, said drain region of said first conductivity type and having a dopant concentration equal to or greater than 10 20 /cm 3 ; a body region between said source and drain regions, said body region of a second conductivity type and having a first dopant level of between about 10 14 /cm 3 and about 10 17 /cm 7 and; a first contact region of said second conductivity type and having a dopant level of between about 10 18 /cm 3 and about 10 19 /cm 3 such that said first contact region has a resistivity lower than that of said body region, said first contact region disposed along substantially the entire width of said body region and between said source region and said body region.

Claim 7

A transistor, comprising: an insulating layer; a semiconductor mesa having a base adjacent said insulating layer, said semiconductor mesa comprising: a source region within said semiconductor mesa, said source region of a first conductivity type and having a dopant concentration equal to or greater than 10 20 /cm 3 ; a drain region within said semiconductor mesa, said drain region of said first conductivity type and having a dopant concentration equal to or greater than 10 20 /cm 3 ; a body region between said source and drain regions, said body region of a second conductivity type and having a first dopant level of between about 10 14 /cm 3 and about 10 17 /cm 7 and; a first contact region of said second conductivity type and having a dopant level of between about 10 18 /cm 3 and about 10 19 /cm 3 such that said first contact region has a resistivity lower than that of said body region, said first contact region disposed along substantially the entire width of said body region and between said source region and said body region.

Claim 8

The transistor of claim 5 and further comprising a second contact region of resistivity lower than that of said body region disposed along substantially the entire width of said body region and adjacent said drain region and said body region and said insulating layer.

Claim 9

The transistor of claim 6 wherein said semiconductor mesa has a top opposite said base and said first contact region is disposed adjacent said insulating layer and has an upper surface below said mesa top, and further comprising a vertical contact region adjoining said first contact region and extending away from said upper surface and toward said top of said semiconductor mesa.

Claim 10

The transistor of claim 7 wherein said vertical contact region is of said second conductivity type and has a dopant level greater than the first dopant level of said body region.

Claim 11

The transistor of claim 8 and further comprising an ohmic contact connecting said source region and said vertical contact region.

Claim 12

The transistor of claim 9 wherein said ohmic contact comprises a silicide contact.

Claim 13

The transistor of claim 5 wherein said first contact region fully separates said source region from said insulating layer.

Claim 14

The transistor of claim 11 wherein said semiconductor mesa has a top opposite said base, and further comprising a vertical contact region away from said body region and adjoining said first contact region and extending toward said top of said semiconductor mesa.

Claim 15

The transistor of claim 12 wherein said vertical contact region is of said second conductivity type and has a dopant level greater than the dopant level of said body region.

Claim 16

The transistor of claim 5 wherein said semiconductor mesa has a top opposite said base, and further comprising: a segment region adjacent said source region and said insulating layer, and further contacting said first contact region; and a vertical contact region adjoining said segment region and extending toward said top of said semiconductor mesa.

Claim 17

The transistor of claim 14 wherein said vertical contact region is of said second conductivity type and has a dopant level greater than the dopant level of said body region.

Claim 18

The transistor of claim 14 wherein said segment region is of said second conductivity type and a dopant level greater than the dopant level of said body region.

Claim 19

The transistor of claim 5 and further comprising a gate conductor adjacent said body region.

Claim 20

The transistor of claim 17 and further comprising an insulating layer between said gate conductor and said body region.

Claim 21

The transistor of claim 5 and further comprising an edge contact adjacent and connected to said body region.

Claim 22

The transistor of claim 19 wherein said edge contact further contacts said first contact region.

Claim 23

The transistor of claim 19 and further comprising a second contact region of resistivity lower than that of said body region disposed along substantially the entire width of said body region and adjacent said drain region, said body region and said insulating layer.

Claim 24

The transistor of claim 21 wherein said edge contact further contacts said first and second contact regions.

Claim 25

A semiconductor over insulator transistor, comprising: an insulating layer; a semiconductor mesa having a base adjacent said insulating layer and a top opposite said base, and having first and second ends, said semiconductor mesa comprising: a source region at said first end of said semiconductor mesa, said source region of a first conductivity type and having a dopant concentration equal to or greater than 10 20 /cm 3 ; a drain region at said second end of said semiconductor mesa, said drain region of said first conductivity type and having a dopant concentration equal to or greater than 10 20 /cm 3 ; a body region between said source and drain regions, said body region of a second conductivity type and of a first dopant level of between 10 14 /cm 3 and about 10 17 /cm 3 ; a first contact region of said second conductivity type and having a dopant level of between about 10 18 /cm 3 and about 10 19 /cm 3 such that said first contact region has a resistivity lower than that of said body region, said first contact region disposed along substantially the entire width of said body region and between said source region and said body region such that voltage applied to said first contact region will be more uniformly distributed across said body region, said first contact region being of said second conductivity type and of a second dopant level greater in dopant concentration than said first dopant level; and a vertical contact region connecting said first contact region and said top of said semiconductor mesa, said vertical contact region being of said second conductivity type and a dopant level greater in dopant concentration than said first dopant level of said body region.

Claim 26

A semiconductor over insulator transistor, comprising: an insulating layer; a semiconductor mesa having a base adjacent said insulating layer and a top opposite said base, and having first and second ends, said semiconductor mesa comprising: a source region at said first end of said semiconductor mesa, said source region of a first conductivity type and having a dopant concentration equal to or greater than 10 20 /cm 3 ; a drain region at said second end of said semiconductor mesa, said drain region of said first conductivity type and having a dopant concentration equal to or greater than 10 20 /cm 3 ; a body region between said source and drain regions, said body region of a second conductivity type and of a first dopant level of between 10 14 /cm 3 and about 10 17 /cm 3 ; a first contact region of said second conductivity type and having a dopant level of between about 10 18 /cm 3 and about 10 19 /cm 3 such that said first contact region has a resistivity lower than that of said body region, said first contact region disposed along substantially the entire width of said body region and between said source region and said body region such that voltage applied to said first contact region will be more uniformly distributed across said body region, said first contact region being of said second conductivity type and of a second dopant level greater in dopant concentration than said first dopant level; and a vertical contact region connecting said first contact region and said top of said semiconductor mesa, said vertical contact region being of said second conductivity type and a dopant level greater in dopant concentration than said first dopant level of said body region.

Claim 27

The semiconductor over insulator transistor of claim 23 and further comprising a second contact region of resistivity lower than that of said body region disposed along substantially the entire width of said body region and adjacent said drain region and said body region, said second contact region being of said second conductivity type and said second dopant level.

Claim 28

The semiconductor over insulator transistor of claim 23 and further comprising a silicide region connecting said source region and said vertical contact region.

Claim 29

The semiconductor over insulator transistor of claim 23 wherein said first contact region extends fully between said source region and said insulating layer such that said source region is separated from said insulating layer.

Claim 30

The semiconductor over insulator transistor of claim 26 wherein said vertical contact region between said first contact region and said top of said semiconductor mesa is away from said body region.

Claim 31

The semiconductor over insulator transistor of claim 23 and further comprising a segment region of said second conductivity type and a dopant level greater than said body region, said segment region adjacent said source region and said insulating layer, and further connecting said vertical contact region to said first contact region.

Claim 32

A transistor, comprising: an insulating layer; a semiconductor mesa having a base adjacent said insulating layer and a top opposite said base, said semiconductor mesa comprising: a source region within said semiconductor mesa, said source region of a first conductivity type; a drain region within said semiconductor mesa, said drain region of said first conductivity type; a body region between said source and drain regions, said body region of a second conductivity type and of a first dopant level; a first contact region of resistivity lower than that of said body region disposed along substantially the entire width of said body region and between said source region and said body region; a segment region adjacent said source region and said insulating layer, and further contacting said first contact region; and a vertical contact region adjoining said segment region and extending toward said top of said semiconductor mesa.

Claim 33

A transistor, comprising: an insulating layer; a semiconductor mesa having a base adjacent said insulating layer and a top opposite said base, said semiconductor mesa comprising: a source region within said semiconductor mesa, said source region of a first conductivity type; a drain region within said semiconductor mesa, said drain region of said first conductivity type; a body region between said source and drain regions, said body region of a second conductivity type and of a first dopant level; a first contact region of resistivity lower than that of said body region disposed along substantially the entire width of said body region and between said source region and said body region; a segment region adjacent said source region and said insulating layer, and further contacting said first contact region; and a vertical contact region adjoining said segment region and extending toward said top of said semiconductor mesa.

Claim 34

The transistor of claim 1 wherein said first contact region is of said second conductivity type and of a second dopant level greater in dopant concentration than said first dopant level.

Claim 35

The transistor of claim 5 and further comprising a second contact region of resistivity lower than that of said body region disposed along substantially the entire width of said body region and adjacent said drain region, said body region and said insulating layer.

Claim 36

The transistor of claim 31 wherein said second contact region is of said second conductivity type and of a second dopant level greater in dopant concentration than said first dopant level.

Claim 37

The transistor of claim 23 and further comprising an ohmic contact connecting said source region and said vertical contact region.

Claim 38

The transistor of claim 33 wherein said ohmic contact comprises a silicide contact.

Claim 39

The transistor of claim 5 wherein said first contact region fully separates said source region from said insulating layer.

Claim 40

The transistor of claim 35 wherein said vertical contact region is spaced from said body region.

Claim 41

The transistor of claim 36 wherein said vertical contact region is of said second conductivity type and of a second dopant level greater in dopant concentration than said first dopant level.

Claim 42

The transistor of claim 5 wherein said transistor is a lightly doped drain transistor.

Claim 43

The transistor of claim 5 and further comprising a gate conductor adjacent said body region.

Claim 44

The transistor of claim 39 and further comprising an insulating layer between said gate conductor and said body region.

Claim 45

The transistor of claim 5 and further comprising an edge contact adjacent and connected to said body region.

Claim 46

The transistor of claim 41 wherein said edge contact further contacts said first contact region.

Claim 47

The transistor of claim 41 and further comprising a second contact region of resistivity lower than that of said body region disposed along substantially the entire width of said body region and adjacent said drain region, said body region and said insulating layer.

Claim 48

The transistor of claim 43 wherein said edge contact further contacts said first and second contact regions.