← Back to Patent Explorer
US4969023A Expired / Lapsed US ⏱️ 0.0 years remaining

SOS transistor structure

Assignee: ABB AB
•
Filing: 1988-08-23
•
Granted: 1990-11-06
•
Expires: 2008-08-23
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A MOS transistor is formed in a silicon layer applied on an insulating base. The channel region of the transistor has a weakly doped region located nearest the surface of the layer and a more heavily doped region nearest the base. The latter region extends in under the source region of the transistor and is connected to the source contact of the transistor via a highly doped region of the same conduction type. The more heavily doped region is doped with a doping dose of at least 2.10 12 cm -2 .

Inventors

  • 👤 Per Svedberg

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 21:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6708; H10D86/00

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 217 words
A MOS transistor formed in a semiconductor layer, and arranged on an insulating base, comprising: a channel region of a first conduction type having a more heavily doped part adjacent to the base and a more weakly doped part extending to the surface of the semiconductor layer; source and drain regions of a second conduction type contiguous to opposite edges of, and separated by, the weakly doped part of the channel region; a source contact being connected to the source region; a drain contact being connected to the drain region; a control electrode being arranged on top of said more weakly doped part of the channel region and separated therefrom by an insulating layer; said channel region and said control electrode extending to opposite edges of said semiconductor layer; wherein said more heavily doped part of the channel region extends under the source region, completely separating the source region from the base; a second region of said first conduction type being arranged contiguous (a) to the source region, (b) to said more heavily doped part of the channel region, and (c) to the surface of the semiconductor layer, said second region and said more heavily doped part of the channel region completely separating the source region from said base and from the edges of the semiconductor layer.
Claim 2
Dependent Claim 217 words
A MOS transistor formed in a semiconductor layer, and arranged on an insulating base, comprising: a channel region of a first conduction type having a more heavily doped part adjacent to the base and a more weakly doped part extending to the surface of the semiconductor layer; source and drain regions of a second conduction type contiguous to opposite edges of, and separated by, the weakly doped part of the channel region; a source contact being connected to the source region; a drain contact being connected to the drain region; a control electrode being arranged on top of said more weakly doped part of the channel region and separated therefrom by an insulating layer; said channel region and said control electrode extending to opposite edges of said semiconductor layer; wherein said more heavily doped part of the channel region extends under the source region, completely separating the source region from the base; a second region of said first conduction type being arranged contiguous (a) to the source region, (b) to said more heavily doped part of the channel region, and (c) to the surface of the semiconductor layer, said second region and said more heavily doped part of the channel region completely separating the source region from said base and from the edges of the semiconductor layer.
Claim 3
Dependent Claim 24 words
MOS transistor according to claim 1, wherein said second region is more heavily doped than said more heavily doped part of the channel region.
Claim 4
Dependent Claim 16 words
MOS transistor according to claim 1, wherein said source contact is connected to said second region.

References Cited (Backward Citations)

JPS51147186A Cited
JPS5727069A Cited
JPS57190362A Cited
JPS5898969A Cited
US4797721A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-11-05 1994-05-07 1994-11-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-11-05 1998-05-07 1998-11-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-11-05 2002-05-07 2002-11-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag