US6281577B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chips arranged in plurality of planes and electrically connected to one another
Assignee: Pac Tech Packaging Technologies GmbH
•
Filing: 1997-04-22
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Granted: 2001-08-28
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Expires: 2017-04-22
Abstract
Abstract Process for the formation of a spatial chip arrangement having several chips ( 32, 36, 37, 38, 39 ) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces ( 33 ) to assigned conducting paths ( 23 ) of a conducting-path structure ( 24, 25 ) arranged on at least one carrier substrate ( 21, 22 ) by the chips being arranged either transverse to the longitudinal extent of the carrier substrate or parallel to the longitudinal extent of the flexibly constructed carrier substrate, as well as a spatial chip arrangement that is formed by means of this process.
Inventors
- 👤 Hans-Hermann Oppermann
- 👤 Elke Zakel
- 👤 Ghassem Azdasht
- 👤 Paul Kasulke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:09
CPC Classifications
H; H10; H10W; H10W90/00; H10W72/00; H10W72/60; H10W72/834; H10W90/20; H10W90/231; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A spacial chip arrangement comprising a plurality of chips arranged in a plurality of planes and electrically connected to one another, the plurality of chips include each a peripheral connection surface; a conducting structure includes a conducting path structure being an integral part of a carrier substrate and having conductive paths; the peripheral connection surfaces are directly electrically connected to assigned conducting paths by melted solder bumps; the connection surfaces are arranged in a plane transverse to the carrier substrate; the conducting path structure is arranged on at least one side of the carrier substrate and extends parallel to a surface plane thereto and the chips being arranged transverse to the carrier substrate; wherein the carrier substrate is formed of a flexible material comprises a plurality of carrier substrates, and wherein the plurality of chips are connected via several rows of peripheral connection surfaces to the plurality of carrier substrates which are assigned respectively to a row of connection surfaces.
Claim 2
Dependent Claim
160 words
A spacial chip arrangement comprising a plurality of chips arranged in a plurality of planes and electrically connected to one another, the plurality of chips include each a peripheral connection surface; a conducting structure includes a conducting path structure being an integral part of a carrier substrate and having conductive paths; the peripheral connection surfaces are directly electrically connected to assigned conducting paths by melted solder bumps; the connection surfaces are arranged in a plane transverse to the carrier substrate; the conducting path structure is arranged on at least one side of the carrier substrate and extends parallel to a surface plane thereto and the chips being arranged transverse to the carrier substrate; wherein the carrier substrate is formed of a flexible material comprises a plurality of carrier substrates, and wherein the plurality of chips are connected via several rows of peripheral connection surfaces to the plurality of carrier substrates which are assigned respectively to a row of connection surfaces.
Claim 3
Dependent Claim
72 words
The spacial chip arrangement according to claim 1 , wherein parallel to one chip, forming an outertermination, a printed circuit board having an external contact-surface arrangement is arranged on its outside and distributed in planar manner is contacted with the conducting paths of the carrier substrate via its internal contacts arranged on periphery of the printed circuit board and connected to the external contact-surface arrangement by means of a connection conducting-path structure.
Claim 4
Dependent Claim
17 words
The spacial chip arrangement according to claim 2 , further comprising spacer devices arranged between the chips.
Claim 5
Dependent Claim
49 words
The spacial chip arrangement according to claim 3 , wherein the chips comprise two peripheral rows of connection surfaces arranged in offset manner in relation to one another and each conducting-path structure comprises a number of conducting paths corresponding to the total number of connection surfaces of both rows.
Claim 6
Dependent Claim
19 words
The spacial chip arrangement according to claim 4 , wherein the carrier substrate is arranged in a winding form.
Claim 7
Dependent Claim
22 words
The spacial chip arrangement according to claim 5 , wherein the chip arrangement is formed into a block by a sealing material.
Claim 8
Dependent Claim
33 words
The spacial chip arrangement according to claim 1 , wherein the conductive paths extends continuously along a side of the carrier substrate and being positioned such as to face the plurality of chips.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-08-27 | 2005-02-26 | 2005-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-27 | 2009-02-26 | 2009-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-27 | 2013-02-26 | 2013-08-28 | $7700.00 | Window Closed / Lapsed |