Patent US6281084B1 successfully refreshed from Google Patents.
US6281084B1
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US
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Disposable spacers for improved array gapfill in high density DRAMs
Assignee: Qimonda AG
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Filing: 1999-08-31
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Granted: 2001-08-28
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Expires: 2019-08-31
Abstract
Abstract There is disclosed the process of forming a gate conductor for a semiconductor device. The process begins with the step of providing a semiconductor substrate having a gate stack formed thereon, the gate stack including a sidewall. Dielectric spacers are formed on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer being of a doped glass material. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacers are then removed.
Inventors
- 👤 Hiroyuki Akatsu
- 👤 Ramachandra Divakaruni
- 👤 Gill Yong Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:41
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01354; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/09; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
94 words
The process of forming gate conductors for improved gapfill in a high density semiconductor memory device comprising the steps of: providing a semiconductor substrate having an array region and a support region, each including gates stacks formed thereon, each gate stack including a sidewall; forming dielectric spacers on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer defining an offset in the support region; implanting ions into the semiconductor substrate outwardly of the dielectric spacers; and removing the outer spacer for improved array gapfill characteristics.
Claim 2
Dependent Claim
94 words
The process of forming gate conductors for improved gapfill in a high density semiconductor memory device comprising the steps of: providing a semiconductor substrate having an array region and a support region, each including gates stacks formed thereon, each gate stack including a sidewall; forming dielectric spacers on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer defining an offset in the support region; implanting ions into the semiconductor substrate outwardly of the dielectric spacers; and removing the outer spacer for improved array gapfill characteristics.
Claim 3
Dependent Claim
15 words
The process of claim 1 wherein the outer spacer is of a doped glass material.
Claim 4
Dependent Claim
17 words
The process of claim 1 wherein thickness of the outer spacer is greater than the inner spacer.
Claim 5
Dependent Claim
24 words
The process of claim 1 wherein the outer spacer is selected from a group consisting of BSG, PSG, BPSG, FSG, F-BSG, ASG and TEOS.
Claim 6
Dependent Claim
40 words
The process of claim 1 wherein the forming step comprises depositing a first layer of dielectric material over the semiconductor substrate and the gate stack and then depositing a second layer of doped glass or TEOS over the first layer.
Claim 7
Dependent Claim
19 words
The process of claim 5 wherein the dielectric material is selected from a group consisting of nitride and oxide.
Claim 8
Dependent Claim
28 words
The process of claim 5 wherein the forming step further comprises the step of etching horizontal surfaces of the first and second layers to form the dielectric spacers.
Claim 9
Dependent Claim
27 words
The process of claim 1 further comprising the step of depositing a barrier layer over the gate conductor stack and the semiconductor substrate following the removing step.
Claim 10
Dependent Claim
13 words
The process of claim 8 wherein the barrier layer comprises a nitride layer.
Claim 11
Dependent Claim
23 words
The process of claim 8 wherein the inner spacer is formed of oxynitride and the barrier layer is formed of plasma enhanced SiN.
Claim 12
Dependent Claim
140 words
The process of forming gate conductors for improved gapfill in a high density semiconductor memory device comprising the steps of: providing a semiconductor substrate having an oxide layer, defining an array region and a support region, and having gate stacks formed thereon each gate stack including a layer of polysilicon on the oxide layer, a conductor material layer on the polysilicon layer and a nitrite cap layer on the conductor material layer, and a nitrite prespacer surrounding at least part of the gate stack to define a gate conductor sidewall; forming dielectric spacers on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer defining an offset in the support region; implanting ions into the semiconductor substrate outwardly of the dielectric spacers; and removing the outer spacers for improved array gapfill characteristics.
Claim 13
Dependent Claim
140 words
The process of forming gate conductors for improved gapfill in a high density semiconductor memory device comprising the steps of: providing a semiconductor substrate having an oxide layer, defining an array region and a support region, and having gate stacks formed thereon each gate stack including a layer of polysilicon on the oxide layer, a conductor material layer on the polysilicon layer and a nitrite cap layer on the conductor material layer, and a nitrite prespacer surrounding at least part of the gate stack to define a gate conductor sidewall; forming dielectric spacers on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer defining an offset in the support region; implanting ions into the semiconductor substrate outwardly of the dielectric spacers; and removing the outer spacers for improved array gapfill characteristics.
Claim 14
Dependent Claim
15 words
The process of claim 11 wherein the outer spacer is of a doped glass material.
Claim 15
Dependent Claim
17 words
The process of claim 11 wherein thickness of the outer spacer is greater than the inner spacer.
Claim 16
Dependent Claim
24 words
The process of claim 11 wherein the outer spacer is selected from a group consisting of BSG, PSG, BPSG, FSG, F-BSG, ASG, and TEOS.
Claim 17
Dependent Claim
40 words
The process of claim 11 wherein the forming step comprises depositing a first layer of dielectric material over the semiconductor substrate and the gate stack and then depositing a second layer of doped glass or TEOS over the first layer.
Claim 18
Dependent Claim
19 words
The process of claim 15 wherein the dielectric material is selected from a group consisting of nitride and oxide.
Claim 19
Dependent Claim
28 words
The process of claim 15 wherein the forming step further comprises the step of etching horizontal surfaces of the first and second layers to form the dielectric spacers.
Claim 20
Dependent Claim
27 words
The process of claim 11 further comprising the step of depositing a barrier layer over the gate conductor stack and the semiconductor substrate following the removing step.
Claim 21
Dependent Claim
13 words
The process of claim 18 wherein the barrier layer comprises a nitride layer.
Claim 22
Dependent Claim
23 words
The process of claim 18 wherein the inner spacer is formed of oxynitride and the barrier layer is formed of plasma enhanced SiN.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-08-27 | 2005-02-26 | 2005-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-27 | 2009-02-26 | 2009-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-27 | 2013-02-26 | 2013-08-28 | $7700.00 | Window Closed / Lapsed |