Method of making a body contacted SOI MOSFET

Claim 1

The method of forming a silicon-on-insulator device having a p-channel body node and body node contact and an n-channel body node and body node contact comprising: providing a first silicon oxide layer on the surface of a semiconductor substrate; depositing a silicon layer over said first silicon oxide layer; forming an n-channel active area and a p-channel active area within said silicon layer wherein said n-channel active area and said p-channel active area are isolated from one another by an isolation area; forming a gate oxide layer over the surface of said silicon layer; depositing a polysilicon layer overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrode over each of said active areas wherein in each said active area, the portion of said active area directly underlying said gate electrode and extending downward to said first silicon oxide layer comprises said body node; oxidizing said polysilicon layer to form a second silicon oxide layer over said gate electrodes; forming first spacers on the sidewalls of said gate electrodes wherein said first spacers contain p-type impurities; forming a first mask over said n-channel active area; removing said first spacers on the sidewalls of said gate electrode in said p-channel area; forming second spacers on the sidewalls of said gate electrode in said p-channel area wherein said second spacers contain n-type impurities; removing said first mask; driving in said impurities within said first and second spacers to form lightly doped areas underlying said first and second spacers within said n-channel and said p-channel active areas wherein said lightly doped areas do not extend all the way downward to said first silicon oxide layer; forming a second mask over said p-channel active area except for a portion where said p-channel body node contact is to be formed; implanting first ions into said active areas not covered by said second mask whereby first source and drain regions are formed in said n-channel active area and whereby said p-channel body node contact region is formed within said p-channel active area wherein said p-channel body node contact region contacts said p-channel body node; forming a third mask over said n-channel active area except for a portion where said n-channel body node contact is to be formed and forming a third mask over said p-channel body node contact region; implanting second ions into said active areas not covered by said third mask whereby second source and drain regions are formed in said p-channel active area and whereby said n-channel body node contact region is formed within said n-channel active area wherein said n-channel body node contact region contacts said n-channel body node; and annealing said semiconductor substrate to complete formation of said silicon-on-insulator device having said body node contact in the manufacture of an integrated circuit.

Claim 2

The method of forming a silicon-on-insulator device having a p-channel body node and body node contact and an n-channel body node and body node contact comprising: providing a first silicon oxide layer on the surface of a semiconductor substrate; depositing a silicon layer over said first silicon oxide layer; forming an n-channel active area and a p-channel active area within said silicon layer wherein said n-channel active area and said p-channel active area are isolated from one another by an isolation area; forming a gate oxide layer over the surface of said silicon layer; depositing a polysilicon layer overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrode over each of said active areas wherein in each said active area, the portion of said active area directly underlying said gate electrode and extending downward to said first silicon oxide layer comprises said body node; oxidizing said polysilicon layer to form a second silicon oxide layer over said gate electrodes; forming first spacers on the sidewalls of said gate electrodes wherein said first spacers contain p-type impurities; forming a first mask over said n-channel active area; removing said first spacers on the sidewalls of said gate electrode in said p-channel area; forming second spacers on the sidewalls of said gate electrode in said p-channel area wherein said second spacers contain n-type impurities; removing said first mask; driving in said impurities within said first and second spacers to form lightly doped areas underlying said first and second spacers within said n-channel and said p-channel active areas wherein said lightly doped areas do not extend all the way downward to said first silicon oxide layer; forming a second mask over said p-channel active area except for a portion where said p-channel body node contact is to be formed; implanting first ions into said active areas not covered by said second mask whereby first source and drain regions are formed in said n-channel active area and whereby said p-channel body node contact region is formed within said p-channel active area wherein said p-channel body node contact region contacts said p-channel body node; forming a third mask over said n-channel active area except for a portion where said n-channel body node contact is to be formed and forming a third mask over said p-channel body node contact region; implanting second ions into said active areas not covered by said third mask whereby second source and drain regions are formed in said p-channel active area and whereby said n-channel body node contact region is formed within said n-channel active area wherein said n-channel body node contact region contacts said n-channel body node; and annealing said semiconductor substrate to complete formation of said silicon-on-insulator device having said body node contact in the manufacture of an integrated circuit.

Claim 13

The method of forming a p-channel and n-channel silicon-on-insulator device having a body node and a body node contact wherein the current flow from source to drain is unaffected by the presence of said body node contact comprising: providing a semiconductor substrate having an insulator layer thereover and a silicon layer overlying said insulator layer; forming an n-channel and a p-channel active area within said silicon layer having an isolation area therebetween; forming a gate oxide layer over the surface of said silicon layer; depositing a polysilicon layer overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrode over each of said active areas wherein in each said active area, the portion of said active area directly underlying said gate electrode and extending downward to said first silicon oxide layer comprises said body node; oxidizing said polysilicon layer to form a second silicon oxide layer over said gate electrodes; forming first spacers on the sidewalls of said gate electrodes wherein said first spacers contain p-type impurities; forming a first mask over said n-channel active area; removing said first spacers on the sidewalls of said gate electrode in said p-channel area; forming second spacers on the sidewalls of said gate electrode in said p-channel area wherein said second spacers contain n-type impurities; removing said first mask; driving in said impurities within said first and second spacers to form lightly doped areas underlying said first and second spacers within said n-channel and said p-channel active areas wherein said lightly doped areas do not extend all the way downward to said insulator layer; forming a second mask over said p-channel active area except for a portion where said p-channel body node contact is to be formed; implanting first ions into said active areas not covered by said second mask whereby first source and drain regions are formed in said n-channel active area and whereby a p-channel body node contact region is formed within a portion of said source region within said p-channel active area wherein said p-channel body node contact region contacts said p-channel body node; forming a third mask over said n-channel active area except for a portion where said n-channel body node contact is to be formed and forming a mask over said p-channel body node contact region; implanting second ions into said active areas not covered by said third mask whereby second source and drain regions are formed in said p-channel active area and whereby an n-channel body node contact region is formed within a portion of said source region in said n-channel active area wherein said n-channel body node contact region contacts said n-channel body node; and annealing said semiconductor substrate to complete formation of said silicon-on-insulator device having said body node contact in the manufacture of an integrated circuit wherein said current flow from said source to said drain is unaffected by the presence of said body node contact because said lightly doped areas serve as source/drain extensions so that said current flow between said source and drain regions is not blocked by said body node contact.

Claim 14

The method of forming a p-channel and n-channel silicon-on-insulator device having a body node and a body node contact wherein the current flow from source to drain is unaffected by the presence of said body node contact comprising: providing a semiconductor substrate having an insulator layer thereover and a silicon layer overlying said insulator layer; forming an n-channel and a p-channel active area within said silicon layer having an isolation area therebetween; forming a gate oxide layer over the surface of said silicon layer; depositing a polysilicon layer overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrode over each of said active areas wherein in each said active area, the portion of said active area directly underlying said gate electrode and extending downward to said first silicon oxide layer comprises said body node; oxidizing said polysilicon layer to form a second silicon oxide layer over said gate electrodes; forming first spacers on the sidewalls of said gate electrodes wherein said first spacers contain p-type impurities; forming a first mask over said n-channel active area; removing said first spacers on the sidewalls of said gate electrode in said p-channel area; forming second spacers on the sidewalls of said gate electrode in said p-channel area wherein said second spacers contain n-type impurities; removing said first mask; driving in said impurities within said first and second spacers to form lightly doped areas underlying said first and second spacers within said n-channel and said p-channel active areas wherein said lightly doped areas do not extend all the way downward to said insulator layer; forming a second mask over said p-channel active area except for a portion where said p-channel body node contact is to be formed; implanting first ions into said active areas not covered by said second mask whereby first source and drain regions are formed in said n-channel active area and whereby a p-channel body node contact region is formed within a portion of said source region within said p-channel active area wherein said p-channel body node contact region contacts said p-channel body node; forming a third mask over said n-channel active area except for a portion where said n-channel body node contact is to be formed and forming a mask over said p-channel body node contact region; implanting second ions into said active areas not covered by said third mask whereby second source and drain regions are formed in said p-channel active area and whereby an n-channel body node contact region is formed within a portion of said source region in said n-channel active area wherein said n-channel body node contact region contacts said n-channel body node; and annealing said semiconductor substrate to complete formation of said silicon-on-insulator device having said body node contact in the manufacture of an integrated circuit wherein said current flow from said source to said drain is unaffected by the presence of said body node contact because said lightly doped areas serve as source/drain extensions so that said current flow between said source and drain regions is not blocked by said body node contact.

Claim 23

A method of forming a p-channel and n-channel silicon-on-insulator device having a body node and a body node contact wherein the current flow from source to drain is unaffected by the presence of said body node contact comprising: providing a semiconductor substrate having an insulator layer thereover and a silicon layer overlying said insulator layer; forming an n-channel and a p-channel active area within said silicon layer having an isolation area therebetween; forming a gate oxide layer over the surface of said silicon layer; depositing a polysilicon layer overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrode over each of said active areas wherein in each said active area, the portion of said active area directly underlying said gate electrode and extending downward to said first silicon oxide layer comprises said body node; oxidizing said polysilicon layer to form a second silicon oxide layer over said gate electrodes; forming first spacers on the sidewalls of said gate electrodes wherein said first spacers contain phosphorus impurities; forming a first mask over said n-channel active area; removing said first spacers on the sidewalls of said gate electrode in said p-channel area; forming second spacers on the sidewalls of said gate electrode in said p-channel area wherein said second spacers contain boron impurities; removing said first mask; driving in said impurities within said first and second spacers to form lightly doped areas underlying said first and second spacers within said n-channel and said p-channel active areas wherein said lightly doped areas do not extend all the way downward to said insulator layer; forming a second mask over said p-channel active area except for a portion where said p-channel body node contact is to be formed; implanting first ions into said active areas not covered by said second mask whereby first source and drain regions are formed in said n-channel active area and whereby a p-channel body node contact region is formed within a portion of said source region within said p-channel active area wherein said p-channel body node contact region contacts said p-channel body node; forming a third mask over said n-channel active area except for a portion where said n-channel body node contact is to be formed and forming a mask over said p-channel body node contact region; implanting second ions into said active areas not covered by said third mask whereby second source and drain regions are formed in said p-channel active area and whereby an n-channel body node contact region is formed within a portion of said source region in said n-channel active area wherein said n-channel body node contact region contacts said n-channel body node; and annealing said semiconductor substrate to complete formation of said silicon-on-insulator device having said body node contact in the manufacture of an integrated circuit wherein said current flow from said source to said drain is unaffected by the presence of said body node contact because said lightly doped areas serve as source/drain extensions so that said current flow between said source and drain regions is not blocked by said body node contact.

Claim 24

A method of forming a p-channel and n-channel silicon-on-insulator device having a body node and a body node contact wherein the current flow from source to drain is unaffected by the presence of said body node contact comprising: providing a semiconductor substrate having an insulator layer thereover and a silicon layer overlying said insulator layer; forming an n-channel and a p-channel active area within said silicon layer having an isolation area therebetween; forming a gate oxide layer over the surface of said silicon layer; depositing a polysilicon layer overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrode over each of said active areas wherein in each said active area, the portion of said active area directly underlying said gate electrode and extending downward to said first silicon oxide layer comprises said body node; oxidizing said polysilicon layer to form a second silicon oxide layer over said gate electrodes; forming first spacers on the sidewalls of said gate electrodes wherein said first spacers contain phosphorus impurities; forming a first mask over said n-channel active area; removing said first spacers on the sidewalls of said gate electrode in said p-channel area; forming second spacers on the sidewalls of said gate electrode in said p-channel area wherein said second spacers contain boron impurities; removing said first mask; driving in said impurities within said first and second spacers to form lightly doped areas underlying said first and second spacers within said n-channel and said p-channel active areas wherein said lightly doped areas do not extend all the way downward to said insulator layer; forming a second mask over said p-channel active area except for a portion where said p-channel body node contact is to be formed; implanting first ions into said active areas not covered by said second mask whereby first source and drain regions are formed in said n-channel active area and whereby a p-channel body node contact region is formed within a portion of said source region within said p-channel active area wherein said p-channel body node contact region contacts said p-channel body node; forming a third mask over said n-channel active area except for a portion where said n-channel body node contact is to be formed and forming a mask over said p-channel body node contact region; implanting second ions into said active areas not covered by said third mask whereby second source and drain regions are formed in said p-channel active area and whereby an n-channel body node contact region is formed within a portion of said source region in said n-channel active area wherein said n-channel body node contact region contacts said n-channel body node; and annealing said semiconductor substrate to complete formation of said silicon-on-insulator device having said body node contact in the manufacture of an integrated circuit wherein said current flow from said source to said drain is unaffected by the presence of said body node contact because said lightly doped areas serve as source/drain extensions so that said current flow between said source and drain regions is not blocked by said body node contact.