US5686331A
Expired / Lapsed
US
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Fabrication method for semiconductor device
Assignee: SK Hynix Inc
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Filing: 1996-12-24
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Granted: 1997-11-11
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Expires: 2016-12-24
Abstract
Abstract A fabrication method for a semiconductor device which is capable of preventing the shorting of the semiconductor device by performing an ion-implantation of an impurity after forming an insulating layer on a gate electrode, and forming sidewall spacers on the upper surface of the gate electrode and at the sides thereof includes: forming on a semiconductor substrate a pattern including a gate insulating film, a gate electrode on the gate insulating film and a disposable layer on the gate electrode; forming low concentration impurity regions in the substrate by performing an ion implantation, using the pattern as a mask; forming first sidewall spacers at the sides of the pattern; forming high concentration impurity regions in the substrate by performing an ion implantation, using the pattern and the sidewall spacers as a mask; stripping the disposable layer; forming second sidewall spacers at the sides of the first sidewall spacers and on both ends of the upper surface of the gate electrode; and forming a reaction layer of a metal and a silicon on the gate electrode and the high concentration impurity regions.
Inventors
- 👤 Du-Heon Song
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:38
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/0223; H10D30/0227; H10D64/015; H10D64/017; H10D64/60; H10D64/66; H10D64/671; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/0137; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
139 words
A fabrication method for a semiconductor device, comprising the steps of: forming on a semiconductor substrate a pattern including a gate insulating film, a gate electrode on the gate insulating film and a disposable layer on the gate electrode; forming low concentration impurity regions in the substrate by performing an ion implantation, using the pattern as a mask; forming first sidewall spacers at sides of the pattern; forming high concentration impurity regions in the substrate by performing an ion implantation, using the pattern and the sidewall spacers as a mask; stripping the disposable layer; forming second sidewall spacers at inner sides of the first sidewall spacers and on both ends of an upper surface of the gate electrode; and forming a reaction layer of a metal and a silicon on the gate electrode and the high concentration impurity regions.
Claim 2
Dependent Claim
139 words
A fabrication method for a semiconductor device, comprising the steps of: forming on a semiconductor substrate a pattern including a gate insulating film, a gate electrode on the gate insulating film and a disposable layer on the gate electrode; forming low concentration impurity regions in the substrate by performing an ion implantation, using the pattern as a mask; forming first sidewall spacers at sides of the pattern; forming high concentration impurity regions in the substrate by performing an ion implantation, using the pattern and the sidewall spacers as a mask; stripping the disposable layer; forming second sidewall spacers at inner sides of the first sidewall spacers and on both ends of an upper surface of the gate electrode; and forming a reaction layer of a metal and a silicon on the gate electrode and the high concentration impurity regions.
Claim 3
Dependent Claim
23 words
The fabrication method of claim 1, wherein the first sidewall spacers have a larger etch selectivity in comparison with the second sidewall spacers.
Claim 4
Dependent Claim
42 words
The fabrication method of claim 1, wherein a silicide is formed at drain/source regions in the semiconductor substrate and a polysilicide is formed in an upper portion in the gate electrode by the reaction of a transfer metal with the semiconductor substrate.
Claim 5
Dependent Claim
27 words
The fabrication method of claim 1, wherein the disposable layer is composed of an oxide film, and the first sidewall spacers are composed of a nitride film.
Claim 6
Dependent Claim
27 words
The fabrication method of claim 1, wherein the disposable layer is composed of a nitride film, and the first sidewall spacers are composed of an oxide film.
Claim 7
Dependent Claim
15 words
The fabrication method of claim 1, wherein the gate electrode are composed of a polysilicon.
Claim 8
Dependent Claim
44 words
The fabrication method of claim 1, wherein the formation of the reaction layer comprises the steps of: performing an ion implantation of a metal on the semiconductor substrate; and reacting the metal with the substrate, and the metal with the gate electrode by annealing.
Claim 9
Dependent Claim
19 words
The fabrication method of claim 7, wherein the metal used is selected from among Co, Mo, W and Ti.
Claim 10
Dependent Claim
14 words
The fabrication method of claim 7, wherein the annealing temperature is about 600°˜850° C.
Claim 11
Dependent Claim
24 words
The fabrication method of claim 7, wherein the temperature of the semiconductor substrate in the metal ion implantation is maintained to be 300°˜400° C.
Claim 12
Dependent Claim
27 words
The fabrication method of claim 7, wherein the metal ions are implanted under the condition that a dosage is about 1-7E15/cm and an energy is 20-30 KeV.
Claim 13
Dependent Claim
22 words
The fabrication method of claim 7, wherein the formation of the reaction layer further comprises stripping the first and second sidewall spacers.
Claim 14
Dependent Claim
67 words
The fabrication method of claim 1, wherein the formation of the reaction layer of a metal and a silicon comprises the steps of: forming a metallic layer on the gate electrode and the substrate including the high concentration impurity regions by a sputtering process after stripping the disposable layer; and reacting the metallic layer with the substrate, and the metallic layer with the gate electrode by annealing.
Claim 15
Dependent Claim
25 words
The fabrication method of claim 13, wherein the formation of the reaction layer further comprises a step of stripping the first and second sidewall spacers.
References Cited (Backward Citations)
US4577392A
Cited
US4885259A
Cited
US5314832A
Cited
US5124280A
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US5340761A
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US5352631A
Cited
US5518960A
Cited
US5405790A
Cited
US5420057A
Cited
US5496750A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-11-10 | 2001-05-12 | 2001-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-10 | 2005-05-12 | 2005-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-10 | 2009-05-12 | 2009-11-11 | $7700.00 | Window Closed / Lapsed |