US5405790A
Expired / Lapsed
US
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Method of forming a semiconductor structure having MOS, bipolar, and varactor devices
Assignee: Motorola Solutions Inc
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Filing: 1993-11-23
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Granted: 1995-04-11
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Expires: 2013-11-23
Abstract
Abstract A varactor (10, 115, 122) is formed using a BICMOS process flow. An N well (28) of a varactor region (13) is formed in an epitaxial layer (22) by doping the epitaxial layer (22) with an N type dopant. A cathode region (55, 132) is formed in the N well (28) by further doping the N well (28) with the N type dopant. Cathode electrodes (91, 114) are formed by patterning a layer of polysilicon (62, 86) over the epitaxial layer (22). Subsequently, the cathode electrodes (91, 114) are doped with an N type dopant. A region adjacent the cathode region (55, 132) is doped to form a lightly doped region (103, 117). The lightly doped region (103, 117) is doped with a P type dopant to form an anode region (109, 119).
Inventors
- 👤 Irfan Rahim
- 👤 Bor-Yuan C. Hwang
- 👤 Julio Costa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:23
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
241 words
A method of fabricating a semiconductor structure having MOS, bipolar, and varactor devices, comprising the steps of: providing an isolation structure having MOS, bipolar, and varactor active areas, each active area including a doped well; forming a first dopant region in the bipolar active area and a second dopant region in the varactor active area; forming a first semiconductor layer over the MOS, bipolar, and varactor active areas; forming an active base region in the bipolar active area doped well; forming a dielectric layer on portions of the first semiconductor layer over the bipolar and the varactor active areas; forming an opening in the dielectric layer, the opening extending to the first semiconductor layer; forming a second semiconductor layer over the MOS, bipolar, and varactor active areas; forming a gate electrode in the MOS active area, emitter and collector electrodes on the bipolar active area, and a first varactor electrode on the varactor active area, wherein the gate, emitter, collector, and first varactor electrodes are formed from the first and second semiconductor layers, and the emitter electrode extends into the opening; doping the emitter, collector, and first varactor electrodes; forming self-aligned source and drain regions in the MOS active area, and a self-aligned varactor dopant region in the varactor active area; forming a second varactor electrode on the varactor active device area; and diffusing an emitter region into the bipolar active area doped well from the emitter electrode through the opening.
Claim 2
Independent Claim
241 words
A method of fabricating a semiconductor structure having MOS, bipolar, and varactor devices, comprising the steps of: providing an isolation structure having MOS, bipolar, and varactor active areas, each active area including a doped well; forming a first dopant region in the bipolar active area and a second dopant region in the varactor active area; forming a first semiconductor layer over the MOS, bipolar, and varactor active areas; forming an active base region in the bipolar active area doped well; forming a dielectric layer on portions of the first semiconductor layer over the bipolar and the varactor active areas; forming an opening in the dielectric layer, the opening extending to the first semiconductor layer; forming a second semiconductor layer over the MOS, bipolar, and varactor active areas; forming a gate electrode in the MOS active area, emitter and collector electrodes on the bipolar active area, and a first varactor electrode on the varactor active area, wherein the gate, emitter, collector, and first varactor electrodes are formed from the first and second semiconductor layers, and the emitter electrode extends into the opening; doping the emitter, collector, and first varactor electrodes; forming self-aligned source and drain regions in the MOS active area, and a self-aligned varactor dopant region in the varactor active area; forming a second varactor electrode on the varactor active device area; and diffusing an emitter region into the bipolar active area doped well from the emitter electrode through the opening.
Claim 3
Dependent Claim
44 words
A method of fabricating a semiconductor structure having MOS, bipolar, and varactor devices as claimed in claim 1, further including the step of forming silicide on the gate, emitter, collector, and first electrodes, and in the source, drain, and the self-aligned varactor dopant region.
Claim 4
Dependent Claim
80 words
A method of fabricating a semiconductor structure having MOS, bipolar, and varactor devices as claimed in claim 1, wherein the second dopant region in the varactor active area extends into the varactor active area a first distance, and the self-aligned varactor dopant region in the varactor active area includes a third dopant region extending into the doped well of the varactor active area a second distance, and a fourth dopant region extending into the third dopant region a third distance.
Claim 5
Dependent Claim
38 words
A method of fabricating a semiconductor structure having MOS, bipolar, and varactor devices as claimed in claim 3, wherein the first distance is greater than the second distance, and the second distance is greater than the third distance.
Claim 6
Dependent Claim
54 words
A method of fabricating a semiconductor structure having MOS, bipolar, and varactor devices as claimed in claim 1, wherein the bipolar and varactor active areas include a buried layer, and the first dopant region in the bipolar active area and the second dopant region in the varactor active area extend to the buried layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-10 | 1998-10-10 | 1999-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-10 | 2002-10-10 | 2003-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-10 | 2006-10-10 | 2007-04-11 | $7700.00 | Window Closed / Lapsed |