Patent US6181569B1 successfully refreshed from Google Patents.
US6181569B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low cost chip size package and method of fabricating the same
Assignee: Individual
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Filing: 1999-06-07
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Granted: 2001-01-30
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Expires: 2019-06-07
Abstract
Abstract A first plurality of metal bumps is formed on a semiconductor wafer containing a plurality of chips, each of the first plurality of bumps being in electrical contact with a contact pad on one of the chips. An encapsulant layer is deposited over the first plurality of metal bumps and then polished to expose a top surface on each of the metal bumps. A second plurality of metal bumps is formed on the exposed top surfaces of the first plurality of plurality of bumps, respectively. The wafer is then sawed to separate the individual chips, yielding semiconductor packages which have the same lateral dimensions as the chips. Alternatively, to facilitate the encapsulation process, the wafer can be sawed into rectangular, multi-chip segments before the encapsulant layer is deposited. After the encapsulant layer has been applied and polished and the second plurality of conductive bumps have been formed, the segments are then separated into individual chips. The first plurality of metal bumps can be deposited directly on the contact pads, with or without an underbump metalization layer, or on metal conductive traces over one or more dielectric layers.
Inventors
- 👤 Kishore K. Chakravorty
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:06
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3436; H10W72/00; H10W72/01; H10W72/019; H10W90/00; H10W90/701; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0364; H05K2201/0379; H05K2201/10; H05K2201/10613; H05K2201/10954; H05K2201/10977; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/656; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/241; H10W72/242; H10W72/251; H10W72/252; H10W72/257; H10W72/29; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/9415; H10W72/942; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W72/957; Y; Y02; Y02P; Y02P70/00; Y02P70/50
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
134 words
A semiconductor chip package comprising: a semiconductor chip having a plurality of contact pads; a first dielectric layer overlying the chip and containing a hole, the hole overlying one of the contact pads; a conductive trace extending from a location inside the hole along a surface of the first dielectric layer, the conductive trace being in electrical contact with the pad; a second dielectric layer overlying the first dielectric layer and conductive trace and containing a second hole, the second hole overlying the trace; a first conductive bump formed in the second hole and extending above the second dielectric layer; an encapsulant layer overlying the second dielectric layer, the first conductive bump extending through the encapsulant layer; and a second conductive bump on top of and in electric contact with the first conductive bump.
Claim 2
Dependent Claim
134 words
A semiconductor chip package comprising: a semiconductor chip having a plurality of contact pads; a first dielectric layer overlying the chip and containing a hole, the hole overlying one of the contact pads; a conductive trace extending from a location inside the hole along a surface of the first dielectric layer, the conductive trace being in electrical contact with the pad; a second dielectric layer overlying the first dielectric layer and conductive trace and containing a second hole, the second hole overlying the trace; a first conductive bump formed in the second hole and extending above the second dielectric layer; an encapsulant layer overlying the second dielectric layer, the first conductive bump extending through the encapsulant layer; and a second conductive bump on top of and in electric contact with the first conductive bump.
Claim 3
Dependent Claim
33 words
The semiconductor chip package of claim 1 wherein a side edge of the first and second dielectric layers and the encapsulant layer is located directly over a side edge of the semiconductor chip.
Claim 4
Dependent Claim
32 words
The semiconductor chip package of claim 1 wherein a side edge of the first and second dielectric layers and the encapsulant layer is coplanar with a side edge of the semiconductor chip.
Claim 5
Dependent Claim
149 words
The semiconductor chip package of claim 1 wherein: the first dielectric layer contains a first plurality of holes, each of the first plurality of holes overlying one of the contact pads; a plurality of conductive traces extend from a location inside the first plurality of holes, respectively, each of the conductive traces being in electrical contact with one of the contact pads; a second dielectric layer contains a second plurality of holes, each of the second plurality of holes overlying one of the traces and being lined with a conductive layer in electrical contact with the trace; a plurality of first conductive bumps are formed in the second plurality of holes, respectively; each of the plurality of first conductive bumps extends through the encapsulant layer; and a plurality of second conductive bumps are formed on top of and in electric contact with the plurality of first conductive bumps, respectively.
Claim 6
Dependent Claim
27 words
The semiconductor chip package of claim 1 wherein the second conductive bump has a flat top portion that is coplanar with a surface of the encapsulant layer.
Claim 7
Dependent Claim
64 words
A semiconductor chip package comprising: a semiconductor chip having a plurality of contact pads; a first conductive bump in electrical contact with the contact pad; an nonconductive encapsulant layer overlying the semiconductor chip and surrounding the conductive bump, the first conductive bump extending through the encapsulant layer; and a second conductive bump on top of and in electric contact with the first conductive bump.
Claim 8
Dependent Claim
64 words
A semiconductor chip package comprising: a semiconductor chip having a plurality of contact pads; a first conductive bump in electrical contact with the contact pad; an nonconductive encapsulant layer overlying the semiconductor chip and surrounding the conductive bump, the first conductive bump extending through the encapsulant layer; and a second conductive bump on top of and in electric contact with the first conductive bump.
Claim 9
Dependent Claim
26 words
The semiconductor chip package of claim 6 wherein a side edge of the encapsulant layer is located directly over a side edge of the semiconductor chip.
Claim 10
Dependent Claim
25 words
The semiconductor chip package of claim 6 wherein a side edge of the encapsulant layer is coplanar with a side edge of the semiconductor chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |