Semiconductor package integral with semiconductor chip

Claim 2

A semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substrate, and a first passivating film formed over an entire surface of said semiconductor substrate and having openings above said pads, and the surface of said first passivating film being flat; a plurality of interconnection lines formed on the surface of said first passivating film, each of said interconnection lines being connected to a respective one of said pads; a second passivating film formed over the entire surface of said first passivating film, wherein the edges of said second passivating film are rounded off, and having through holes each located only above a respective one of said interconnection lines, said through holes being arranged in the form of an array and the surface of said second passivating film being flat; and a plurality of contacts for connection to external leads, each of said contacts being formed within and above a respective one of said through holes and said contacts being arranged in the form of an array, wherein said external leads are directly connected to a printed-circuit board.

Claim 3

The semiconductor package according to claim 1, wherein said plurality of pads is placed along the edges of said semiconductor substrate.

Claim 4

The semiconductor package according to claim 1, wherein said plurality of pads is placed evenly over the entire surface of said semiconductor substrate.

Claim 5

The semiconductor package according to claim 1, wherein the edges of said semiconductor substrate coincide with the edges of said first passivating film.

Claim 6

The semiconductor package according to claim 1, wherein each of said interconnection lines is made of one of conductors including aluminum and copper.

Claim 7

The semiconductor package according to claim 1, wherein said second passivating film functions as a package and has a thickness in the range of 0.05 to 0.2 mm.

Claim 8

The semiconductor package according to claim 1, wherein each of said first and second passivating films is made of one of insulating materials including silicon oxide and silicon nitride.

Claim 9

The semiconductor package according to claim 1, wherein, when viewed from above said semiconductor substrate, said contacts are placed symmetrically with respect to the central point of said second passivating film.

Claim 10

The semiconductor package according to claim 1, wherein said contacts are placed evenly over the entire surface of said second passivating film.

Claim 11

The semiconductor package according to claim 1, wherein said contacts are placed along the edges of said second passivating film.

Claim 12

The semiconductor package according to claim 1, wherein, when viewed from above said semiconductor substrate, each of said contacts has a circular shape.

Claim 13

The semiconductor package according to claim 1, wherein, when viewed from above said semiconductor substrate, said semiconductor substrate has a square shape and measures 13.5 mm on a side, each of said contacts has a circular shape with a diameter of 0.5 mm, and the pitch of said contacts is 1 mm.

Claim 14

The semiconductor package according to claim 1, wherein each of said contacts is made of one of conductors including copper, gold, nickel, and a two-layered structure of nickel and gold.

Claim 15

The semiconductor package according to claim 1, further comprising solder balls each formed on a respective one of said contacts.

Claim 16

The semiconductor package according to claim 1, wherein a bottom surface of the semiconductor package comprises a bottom surface of the semiconductor substrate.

Claim 17

A semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substrate, and a first passivating film formed over an entire surface of said semiconductor substrate and having openings above said pads, the surface of said first passivating film being flat, and when viewed from above said semiconductor substrate, the edges of said first passivating film being inside the edges of said semiconductor substrate; a plurality of interconnection lines formed on the surface of said first passivating film, each of said interconnection lines being connected to a respective one of said pads; a second passivating film overlying the edges of said semiconductor substrate and the entire surface and sides of said first passivating film and having through holes each located only above a respective one of said interconnection lines, said through holes being arranged in the form of an array and the surface of said second passivating film being flat; and a plurality of contacts for connection to external leads, each of said contacts being formed within and above a respective one of said through holes and said contacts being arranged in the form of an array, wherein said external leads are directly connected to a printed-circuit board.

Claim 18

A semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substrate, and a first passivating film formed over an entire surface of said semiconductor substrate and having openings above said pads, the surface of said first passivating film being flat, and when viewed from above said semiconductor substrate, the edges of said first passivating film being inside the edges of said semiconductor substrate; a plurality of interconnection lines formed on the surface of said first passivating film, each of said interconnection lines being connected to a respective one of said pads; a second passivating film overlying the edges of said semiconductor substrate and the entire surface and sides of said first passivating film and having through holes each located only above a respective one of said interconnection lines, said through holes being arranged in the form of an array and the surface of said second passivating film being flat; and a plurality of contacts for connection to external leads, each of said contacts being formed within and above a respective one of said through holes and said contacts being arranged in the form of an array, wherein said external leads are directly connected to a printed-circuit board.

Claim 19

The semiconductor package according to claim 16, wherein said plurality of pads is placed along the edges of said semiconductor substrate.

Claim 20

The semiconductor package according to claim 16, wherein said plurality of pads is placed evenly over the entire surface of said semiconductor substrate.

Claim 21

The semiconductor package according to claim 16, wherein the edges of said semiconductor substrate coincide with the edges of said second passivating film.

Claim 22

The semiconductor package according to claim 16, wherein each of said interconnection lines is made of one of conductors including aluminum and copper.

Claim 23

The semiconductor package according to claim 16, wherein said second passivating film functions as a package and has a thickness in the range of 0.05 to 0.2 mm.

Claim 24

The semiconductor package according to claim 16, wherein the edges of said second passivating film are rounded off.

Claim 25

The semiconductor package according to claim 16, wherein each of said first and second passivating films is made of one of insulating materials including silicon oxide and silicon nitride.

Claim 26

The semiconductor package according to claim 16, wherein, when viewed from above said semiconductor substrate, said contacts are placed symmetrically with respect to the central point of said second passivating film.

Claim 27

The semiconductor package according to claim 16, wherein said contacts are placed evenly over the entire surface of said second passivating film.

Claim 28

The semiconductor package according to claim 16, wherein said contacts are placed along the edges of said second passivating film.

Claim 29

The semiconductor package according to claim 16, wherein, when viewed from above said semiconductor substrate, each of said contacts has a circular shape.

Claim 30

The semiconductor package according to claim 16, wherein, when viewed from above said semiconductor substrate, said semiconductor substrate has a square shape and measures 13.5 mm on a side, each of said contacts has a circular shape with a diameter of 0.5 mm, and the pitch of said contacts is 1 mm.

Claim 31

The semiconductor package according to claim 16, wherein each of said contacts is made of one of conductors including copper, gold, nickel, and a two-layered structure of nickel and gold.

Claim 32

The semiconductor package according to claim 16, further comprising solder balls each formed on a respective one of said contacts.

Claim 33

The semiconductor package according to claim 16, wherein a bottom surface of the semiconductor package comprises a bottom surface of the semiconductor substrate.

Claim 34

A semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substrate, and a first passivating film formed over an entire surface of said semiconductor substrate and having openings above said pads, the surface of said first passivating film being flat, the edges of said first passivating film being inside the edges of said semiconductor substrate when viewed from above said semiconductor substrate, and a groove being formed in portions of said semiconductor substrate which are located between the edges of said first passivating film and the edges of said semiconductor substrate; a plurality of interconnection lines formed on the surface of said first passivating film, each of said interconnection lines being connected to a respective one of said pads; a second passivating film overlying the edges of said semiconductor substrate and the entire surface and sides of said first passivating film and having through holes each located only above said a respective one of said interconnection lines, said through holes being arranged in the form of an array and the surface of said second passivating film being flat; and a plurality of contacts for connection to external leads, each of said contacts being formed within and above a respective one of said through holes and said contacts being arranged in the form of an array, wherein said external leads are directly connected to a printed-circuit board.

Claim 35

A semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substrate, and a first passivating film formed over an entire surface of said semiconductor substrate and having openings above said pads, the surface of said first passivating film being flat, the edges of said first passivating film being inside the edges of said semiconductor substrate when viewed from above said semiconductor substrate, and a groove being formed in portions of said semiconductor substrate which are located between the edges of said first passivating film and the edges of said semiconductor substrate; a plurality of interconnection lines formed on the surface of said first passivating film, each of said interconnection lines being connected to a respective one of said pads; a second passivating film overlying the edges of said semiconductor substrate and the entire surface and sides of said first passivating film and having through holes each located only above said a respective one of said interconnection lines, said through holes being arranged in the form of an array and the surface of said second passivating film being flat; and a plurality of contacts for connection to external leads, each of said contacts being formed within and above a respective one of said through holes and said contacts being arranged in the form of an array, wherein said external leads are directly connected to a printed-circuit board.

Claim 36

The semiconductor package according to claim 32, wherein said plurality of pads is placed along the edges of said semiconductor substrate.

Claim 37

The semiconductor package according to claim 32, wherein said plurality of pads is placed evenly over the entire surface of said semiconductor substrate.

Claim 38

The semiconductor package according to claim 32, wherein the edges of said semiconductor substrate coincide with the edges of said second passivating film.

Claim 39

The semiconductor package according to claim 32, wherein each of said interconnection lines is made of one of conductors including aluminum and copper.

Claim 40

The semiconductor package according to claim 32, wherein said second passivating film functions as a package and has a thickness in the range of 0.05 to 0.2 mm.

Claim 41

The semiconductor package according to claim 32, wherein the edges of said second passivating film are rounded off.

Claim 42

The semiconductor package according to claim 32, wherein each of said first and second passivating films is made of one of insulating materials including silicon oxide and silicon nitride.

Claim 43

The semiconductor package according to claim 32, wherein, when viewed from above said semiconductor substrate, said contacts are placed symmetrically with respect to the central point of said second passivating film.

Claim 44

The semiconductor package according to claim 32, wherein said contacts are placed evenly over the entire surface of said second passivating film.

Claim 45

The semiconductor package according to claim 32, wherein said contacts are placed along the edges of said second passivating film.

Claim 46

The semiconductor package according to claim 32, wherein, when viewed from above said semiconductor substrate, each of said contacts has a circular shape.

Claim 47

The semiconductor package according to claim 32, wherein, when viewed from above said semiconductor substrate, said semiconductor substrate has a square shape and measures 13.5 mm on a side, each of said contacts has a circular shape with a diameter of 0.5 mm, and the pitch of said contacts is 1 mm.

Claim 48

The semiconductor package according to claim 32, wherein each of said contacts is made of one of conductors including copper, gold, nickel, and a two-layered structure of nickel and gold.

Claim 49

The semiconductor package according to claim 32, further comprising solder balls each formed on a respective one of said contacts.

Claim 50

The semiconductor package according to claim 32, wherein a bottom surface of the semiconductor package comprises a bottom surface of the semiconductor substrate.

Claim 51

A semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substrate, and a first passivating film formed over an entire surface of said semiconductor substrate and having openings above said pads, and the surface of said first passivating film being flat; a plurality of interconnection lines formed on the surface of said first passivating film, each of said interconnection lines being connected to a respective one of said pads; a second passivating film formed over the entire surface of said first passivating film, wherein the edges of said second passivating film are rounded off, and having through holes each located only above a respective one of said interconnection lines, said through holes being arranged in the form of an array and the surface of said second passivating film being flat; a metal layer formed on the bottom and sides of each of said through holes; and a plated layer formed within and above each of said through holes, said plated layer forming each of contacts for connection to external leads above a respective one of said through holes, wherein said external leads are directly connected to a printed-circuit board.

Claim 52

A semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substrate, and a first passivating film formed over an entire surface of said semiconductor substrate and having openings above said pads, and the surface of said first passivating film being flat; a plurality of interconnection lines formed on the surface of said first passivating film, each of said interconnection lines being connected to a respective one of said pads; a second passivating film formed over the entire surface of said first passivating film, wherein the edges of said second passivating film are rounded off, and having through holes each located only above a respective one of said interconnection lines, said through holes being arranged in the form of an array and the surface of said second passivating film being flat; a metal layer formed on the bottom and sides of each of said through holes; and a plated layer formed within and above each of said through holes, said plated layer forming each of contacts for connection to external leads above a respective one of said through holes, wherein said external leads are directly connected to a printed-circuit board.

Claim 53

The semiconductor package according to claim 46, wherein said plurality of pads is placed along the edges of said semiconductor substrate.

Claim 54

The semiconductor package according to claim 46, wherein said plurality of pads is placed evenly over the entire surface of said semiconductor substrate.

Claim 55

The semiconductor package according to claim 46, wherein the edges of said semiconductor substrate are inside the edges of said second passivating film.

Claim 56

The semiconductor package according to claim 46, wherein each of said interconnection lines is made of one of conductors including aluminum and copper.

Claim 57

The semiconductor package according to claim 46, wherein said second passivating film functions as a package and has a thickness in the range of 0.05 to 0.2 mm.

Claim 58

The semiconductor package according to claim 46, wherein each of said first and second passivating films is made of one of insulating materials including silicon oxide and silicon nitride.

Claim 59

The semiconductor package according to claim 46, wherein, when viewed from above said semiconductor substrate, said contacts are placed symmetrically with respect to the central point of said second passivating film.

Claim 60

The semiconductor package according to claim 46, wherein said contacts are placed evenly over the entire surface of said second passivating film.

Claim 61

The semiconductor package according to claim 46, wherein said contacts are placed along the edges of said second passivating film.

Claim 62

The semiconductor package according to claim 46, wherein, when viewed from above said semiconductor substrate, each of said contacts has a circular shape.

Claim 63

The semiconductor package according to claim 46, wherein, when viewed from above said semiconductor substrate, said semiconductor substrate has a square shape and measures 13.5 mm on a side, each of said contacts has a circular shape with a diameter of 0.5 mm, and the pitch of said contacts is 1 mm.

Claim 64

The semiconductor package according to claim 46, wherein said metal layer is made of at least one of metals including titanium, nickel, and palladium.

Claim 65

The semiconductor package according to claim 46, wherein each of said contacts is made of one of conductors including copper, gold, nickel, and a two-layered structure of nickel and gold.

Claim 66

The semiconductor package according to claim 46, further comprising solder balls each formed on a respective one of said contacts.

Claim 67

The semiconductor package according to claim 48, wherein a bottom surface of the semiconductor package comprises a bottom surface of the semiconductor substrate.