US5360988A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device and methods for production thereof
Assignee: Hitachi Ltd
•
Filing: 1992-06-23
•
Granted: 1994-11-01
•
Expires: 2012-06-23
Abstract
Abstract Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.
Inventors
- 👤 Takayuki Uda
- 👤 Toshiro Hiramoto
- 👤 Nobuo Tamba
- 👤 Hisashi Ishida
- 👤 Kazuhiro Akimoto
- 👤 Masanori Odaka
- 👤 Tasuku Tanaka
- 👤 Jun Hirokawa
- 👤 Masayuki Ohayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:28
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/153; H10W70/00; H10W70/60; H10W72/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/07251; H10W72/20; H10W72/241; H10W72/242; H10W72/251; H10W72/252; H10W72/29; H10W72/851; H10W72/874; H10W72/877; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/9415; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W74/00; H10W74/10; H10W74/131; H10W74/137
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
184 words
A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; a plurality of memory cells formed on said main surface of semiconductor substrate, said plurality of memory cells being arranged in a row direction and a column direction; redundancy memory cells formed on said main surface of semiconductor substrate, being adjacent to said plurality of memory cells; a peripheral circuit formed on said main surface of semiconductor substrate; wirings formed over said peripheral circuit; a protective insulation film formed over said wirings; a barrier metal layer formed on said protective insulation film, said barrier metal layer being connected to one of said wirings via a first contact hole formed in said protective insulation film, said barrier metal layer comprising laminated metal layers; a bump electrode formed on said barrier metal layer; and a fuse element formed on said protective insulation film, said fuse element being used for substituting a fault memory cell for said redundancy memory cells, wherein said fuse element is comprised of the same layer as at least one of said laminated metal layers of said barrier metal layer.
Claim 2
Dependent Claim
184 words
A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; a plurality of memory cells formed on said main surface of semiconductor substrate, said plurality of memory cells being arranged in a row direction and a column direction; redundancy memory cells formed on said main surface of semiconductor substrate, being adjacent to said plurality of memory cells; a peripheral circuit formed on said main surface of semiconductor substrate; wirings formed over said peripheral circuit; a protective insulation film formed over said wirings; a barrier metal layer formed on said protective insulation film, said barrier metal layer being connected to one of said wirings via a first contact hole formed in said protective insulation film, said barrier metal layer comprising laminated metal layers; a bump electrode formed on said barrier metal layer; and a fuse element formed on said protective insulation film, said fuse element being used for substituting a fault memory cell for said redundancy memory cells, wherein said fuse element is comprised of the same layer as at least one of said laminated metal layers of said barrier metal layer.
Claim 3
Dependent Claim
41 words
A semiconductor integrated circuit device according to claim 1, wherein said fuse element is connected to another ones of said wirings at both end portions of said fuse element via second and third contact holes formed in said protective insulation film.
Claim 4
Dependent Claim
46 words
A semiconductor integrated circuit device according to claim 2, further including multiple layered wirings formed over said main surface of said substrate, wherein said multiple layered wirings comprises said wirings formed over said peripheral circuit, and wherein said protective insulation film covers said multiple layered wirings.
Claim 5
Dependent Claim
42 words
A semiconductor integrated circuit device according to claim 3, wherein said one of wirings and said another ones of wirings are positioned at an upper most level in said multiple layered wirings, with respect to said main surface of said semiconductor substrate.
Claim 6
Dependent Claim
51 words
A semiconductor integrated circuit device according to claim 4, wherein said peripheral circuit includes a plurality of semiconductor elements which are electrically connected each other by said multiple layered wirings, and wherein said bump electrode is used as an external terminal for electrically connecting said peripheral circuit to an external device.
Claim 7
Dependent Claim
35 words
A semiconductor integrated circuit device according to claim 4, wherein an energy beam shielding layer for shielding an energy beam for cutting said fuse element is formed under a central portion of said fuse element.
Claim 8
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 6, wherein said energy beam shielding layer is either of said another ones of wirings, and wherein a predetermined potential level is supplied with said energy beam shielding layer.
Claim 9
Dependent Claim
75 words
A semiconductor integrated circuit device according to claim 1, wherein at least one of said laminated metal layers of said barrier metal layer is a chromium film which is positioned at the most lower level in said laminated metal layers, with respect to said main surface of said semiconductor substrate, and wherein said fuse element is comprised of the same layer as said chromium film of said laminated metal layers of said barrier metal layer.
Claim 10
Dependent Claim
81 words
A semiconductor integrated circuit device according to claim 8, wherein said laminated metal layers of said barrier metal layer further include a copper film stacked on said chromium film, and a gold film stacked on said copper film, wherein said fuse element is comprised of the same layers as said copper film and said gold film, and wherein said copper film and said gold film of said fuse element are selectively firmed at the both end portions of said fuse element.
Claim 11
Dependent Claim
29 words
A semiconductor integrated circuit device according to claim 8, wherein said bump electrode is made of a Pb-Sn alloy, and said one of wirings is made of an Al-alloy.
Claim 12
Dependent Claim
19 words
A semiconductor integrated circuit device according to claim 1, wherein said bump electrode is a tape automated bonding bump.
Claim 13
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 1, wherein said bump electrode is a controlled collapse bump.
Claim 14
Dependent Claim
19 words
A semiconductor integrated circuit device according to claim 12, wherein said fuse element is constituted by a transition metal.
Claim 15
Dependent Claim
68 words
A semiconductor integrated circuit device according to claim 12, further comprising a guard ring and a fourth contact hole formed in said protective insulation film, wherein each of said guard ring and said fourth contact hole has a shape surrounding said fuse element in a plane view, and wherein said guard ring is electrically connected to said wirings under said protective insulation film via said fourth contact hole.
References Cited (Backward Citations)
US4346459A
Cited
US4703436A
Cited
JPS62119938A
Cited
US4869170A
Cited
US5017510A
Cited
US5026664A
Cited
US5143865A
Cited
US5027188A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |