US5684330A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chip-sized package having metal circuit substrate
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-11-30
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Granted: 1997-11-04
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Expires: 2015-11-30
Abstract
Abstract A chip-sized semiconductor package having a semiconductor chip formed with bonding pads; a circuit board provided with contact pads for electrically connecting the circuit board to external terminals, and circuit patterns for electrically connecting the circuit board to the chip; a tape bonding the circuit board to the chip; and wires electrically connecting the circuit board to the bonding pads on the chip; the package being encapsulated by a molding compound so that a part of a surface of the circuit board where the contact pads are formed is exposed.
Inventors
- 👤 Sang Hyuk Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 00:58
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/688; H10W76/00; H10W76/10; H10W76/12; H10W70/40; H10W70/411; H10W70/415; H10W70/68; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/851; H10W72/853; H10W72/865; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
195 words
A chip-sized semiconductor package, comprising: a semiconductor chip having a plurality of bonding pads centrally formed thereon; a circuit board having at least one metal layer, at least one electrically non-conductive layer formed on said metal layer, and a plurality of circuit patterns formed on said electrically non-conductive layer, each circuit pattern having a contact pad, said circuit board having an outer perimeter; a tape bonding said circuit board to said semiconductor chip; a plurality of wires electrically connecting respective ones of said circuit patterns of said circuit board to respective ones of said bonding pads of said semiconductor chip; and a molding compound encapsulating said semiconductor chip and said plurality of wires; said circuit board being stepped adjacent said outer perimeter thereof so as to have an uplifted outer perimetrical bordering surface and a sunk central surface; said uplifted outer perimetrical bordering surface having said plurality of contact pads, for being electrically connected to external terminals; said sunk central surface having said plurality of circuit patterns, for being electrically connected to said bonding pads of said semiconductor chip; and said molding compound partially encapsulating said circuit board, so that said contact pads remain exposed.
Claim 2
Dependent Claim
195 words
A chip-sized semiconductor package, comprising: a semiconductor chip having a plurality of bonding pads centrally formed thereon; a circuit board having at least one metal layer, at least one electrically non-conductive layer formed on said metal layer, and a plurality of circuit patterns formed on said electrically non-conductive layer, each circuit pattern having a contact pad, said circuit board having an outer perimeter; a tape bonding said circuit board to said semiconductor chip; a plurality of wires electrically connecting respective ones of said circuit patterns of said circuit board to respective ones of said bonding pads of said semiconductor chip; and a molding compound encapsulating said semiconductor chip and said plurality of wires; said circuit board being stepped adjacent said outer perimeter thereof so as to have an uplifted outer perimetrical bordering surface and a sunk central surface; said uplifted outer perimetrical bordering surface having said plurality of contact pads, for being electrically connected to external terminals; said sunk central surface having said plurality of circuit patterns, for being electrically connected to said bonding pads of said semiconductor chip; and said molding compound partially encapsulating said circuit board, so that said contact pads remain exposed.
Claim 3
Dependent Claim
37 words
The chip-sized semiconductor package of claim 1, further comprising: a hole centrally formed through said circuit board, through said sunk central surface; said wires electrically connecting said circuit patterns to said bonding pads extending through said hole.
Claim 4
Dependent Claim
23 words
The chip-sized semiconductor package of claim 1, wherein: said contact pads are arranged to be soldered for connecting said package to external terminals.
Claim 5
Dependent Claim
189 words
The chip-sized semiconductor package, comprising: a semiconductor chip having a plurality of bonding pads peripherally formed thereon: a circuit board having at least one metal layer, at least one electrically non-conductive layer formed on said metal layer, and a plurality of circuit patterns formed on said electrically non-conductive layer, each circuit pattern having a contact pad, said circuit board having an outer perimeter; a tape bonding said circuit board to said semiconductor chip; a plurality of wires electrically connecting said circuit patterns of said circuit board to said bonding pads of said semiconductor chip; and a molding compound encapsulating said semiconductor chip and said plurality of wires; said circuit board being stepped adjacent said outer perimeter thereof so as to have an uplifted central surface and a sunk outer perimetrical bordering surface; said uplifted central surface having said plurality of contact pads, for being electrically connected to external terminals; said sunk outer perimetrical bordering surface having said plurality of circuit patterns, for being electrically connected to said bonding pads of said semiconductor chip; and said molding compound partially encapsulating said circuit board so that said contact pads remain exposed.
Claim 6
Dependent Claim
189 words
The chip-sized semiconductor package, comprising: a semiconductor chip having a plurality of bonding pads peripherally formed thereon: a circuit board having at least one metal layer, at least one electrically non-conductive layer formed on said metal layer, and a plurality of circuit patterns formed on said electrically non-conductive layer, each circuit pattern having a contact pad, said circuit board having an outer perimeter; a tape bonding said circuit board to said semiconductor chip; a plurality of wires electrically connecting said circuit patterns of said circuit board to said bonding pads of said semiconductor chip; and a molding compound encapsulating said semiconductor chip and said plurality of wires; said circuit board being stepped adjacent said outer perimeter thereof so as to have an uplifted central surface and a sunk outer perimetrical bordering surface; said uplifted central surface having said plurality of contact pads, for being electrically connected to external terminals; said sunk outer perimetrical bordering surface having said plurality of circuit patterns, for being electrically connected to said bonding pads of said semiconductor chip; and said molding compound partially encapsulating said circuit board so that said contact pads remain exposed.
Claim 7
Dependent Claim
23 words
The chip-sized semiconductor package of claim 4, wherein: said contact pads are arranged to be soldered for connecting said package to external terminals.
Claim 8
Dependent Claim
28 words
The chip-sized semiconductor package of claim 4, wherein: said circuit board has a perimetrical confronting said semiconductor chip size which is smaller than that of said semiconductor chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-03 | 2001-05-05 | 2001-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-03 | 2005-05-05 | 2005-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-03 | 2009-05-05 | 2009-11-04 | $7700.00 | Window Closed / Lapsed |