Patent US6181004B1 successfully refreshed from Google Patents.
US6181004B1
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US
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Digital signal processing assembly and test method
Assignee: Sanmina Corp
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Filing: 1999-01-22
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Granted: 2001-01-30
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Expires: 2019-01-22
Abstract
Abstract A printed circuit module supports host processors and memories. The module permits easy upgrades and repairs of the semiconductor devices without requiring modification of the motherboard. The module includes a multilayer printed circuit board with a symmetrical design, permitting chips to be placed on both sides of the board. Microvias connect the contact points on a signal layer directly to a ground layer on the printed circuit board, thereby reducing the need for escape routing. This greatly simplifies the design layout of the module, The ground layer is located between two signal layers, thereby decreasing the crosstalk between the signal layers. The symmetrical design permits drilled vias to extend from a quadrant of one chip and exit through a similar quadrant on the opposite side of the circuit board. The modular design also simplifies impedance matching. Testing of the module may also be accomplished even when the module is not fully populated through the use of test bypass circuitry.
Inventors
- 👤 Jerry D. Koontz
- 👤 Donald F. Coffin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:33
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0266; H05K1/0268; H05K1/0213; H05K1/0216; H05K1/11; H05K1/111; H05K1/112; H05K1/0254; H05K1/0262; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09218; H05K2201/09227; H05K2201/0929; H05K2201/09327; H05K2201/10; H05K2201/10227; H05K2201/10363; H05K2201/10613; H05K2201/10621; H05K2201/10689; H05K2201/10734; H05K2203/00; H05K2203/15; H05K2203/1572; H10; H10W; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
87 words
A method of testing integrated circuits mounted on a printed circuit board comprising the steps of: linking a plurality of footprints to create a test path having an input and an output, wherein each of said plurality of footprints has a test input and a test output; inserting a test bypass element between said test input and said test output of each of said plurality of footprints not populated by an integrated circuit; and applying a test vector to the test input pin of said test path.
Claim 2
Independent Claim
87 words
A method of testing integrated circuits mounted on a printed circuit board comprising the steps of: linking a plurality of footprints to create a test path having an input and an output, wherein each of said plurality of footprints has a test input and a test output; inserting a test bypass element between said test input and said test output of each of said plurality of footprints not populated by an integrated circuit; and applying a test vector to the test input pin of said test path.
Claim 3
Dependent Claim
30 words
The method of claim 1 , further comprising the step of connecting said input of said test path to a pin of an edge connector of said printed circuit board.
Claim 4
Dependent Claim
30 words
The method of claim 1 , further comprising the step of connecting said output of said test path to a pin of an edge connector of said printed circuit board.
Claim 5
Dependent Claim
17 words
The method of claim 1 , wherein the testing of the integrated circuits is performed using JTAG.
Claim 6
Dependent Claim
16 words
The method of claim 1 , wherein the test bypass element is a zero ohm resistor.
Claim 7
Dependent Claim
21 words
The method of claim 1 , wherein the test path is a series path connecting each of the plurality of footprints.
Claim 8
Dependent Claim
16 words
The method of claim 2 , wherein the printed circuit board has 72 edge connector pinouts.
Claim 9
Dependent Claim
16 words
The method of claim 2 , wherein the printed circuit board has 80 edge connector pinouts.
Claim 10
Dependent Claim
22 words
The method of claim 8 , wherein the input of said test path is connected to pin 75 of the edge connector.
Claim 11
Dependent Claim
22 words
The method of claim 8 , wherein the output of said test path is connected to pin 76 of the edge connector.
Claim 12
Dependent Claim
84 words
A multilayer printed circuit board comprising: a first signal layer having a first plurality of signal lines and a second signal layer having a second plurality of signal lines, wherein a signal travels from one of the first plurality of signal lines to one of said second plurality of signal lines without encountering a substantial change in impedance; and a ground layer between said first signal layer and said second signal layer, said ground layer reducing crosstalk between said first and second signal layers.
Claim 13
Dependent Claim
84 words
A multilayer printed circuit board comprising: a first signal layer having a first plurality of signal lines and a second signal layer having a second plurality of signal lines, wherein a signal travels from one of the first plurality of signal lines to one of said second plurality of signal lines without encountering a substantial change in impedance; and a ground layer between said first signal layer and said second signal layer, said ground layer reducing crosstalk between said first and second signal layers.
Claim 14
Dependent Claim
30 words
The multilayer printed circuit board of claim 11 , wherein one of said plurality of signal lines may extend substantially across said second signal layer to form a bus line.
Claim 15
Dependent Claim
21 words
The multilayer printed circuit board of claim 12 , wherein said one of said plurality of signal lines is substantially straight.
Claim 16
Dependent Claim
30 words
The multilayer printed circuit board of claim 11 , wherein the first and second signal layers and the ground layer are individual conductive layers of a plurality of conductive layers.
Claim 17
Dependent Claim
40 words
The multilayer printed circuit board of claim 14 , wherein each of said plurality of conductive layers extending from a top of the printed circuit board has a corresponding symmetrical layer extending from a bottom of the printed circuit board.
Claim 18
Dependent Claim
23 words
The multilayer printed circuit board of claim 11 , wherein an insulation layer is positioned between two of said plurality of conductive layers.
Claim 19
Dependent Claim
208 words
A printed circuit board having at least twelve footprints capable of mounting integrated circuits, said printed circuit board comprising: a plurality of conductive layers; a plurality of insulation layers, wherein each of the plurality of conductive layers is separated by one of said plurality of insulation layers, said layers having dimensions of approximately 11.43 centimeters in length and approximately 2.5 centimeters in height; a first plurality of surface mount pads within said footprints adapted to mount half of said at least twelve integrated circuits on a first of said plurality of conductive layers, wherein said first of said plurality of conductive layers forms a top signal layer of said printed circuit board; a second plurality of surface mount pads within said footprints adapted to mount half of said at least twelve integrated circuits on a second of said plurality of conductive layers, wherein said second of said plurality of conductive layers forms a bottom signal layer of said printed circuit board; and a plurality of microvias within each of said first and second plurality of surface mount pads, wherein each of said plurality of microvias directly electrically connects either said top signal layer to a first ground layer or said bottom signal layer to a second ground layer.
Claim 20
Dependent Claim
208 words
A printed circuit board having at least twelve footprints capable of mounting integrated circuits, said printed circuit board comprising: a plurality of conductive layers; a plurality of insulation layers, wherein each of the plurality of conductive layers is separated by one of said plurality of insulation layers, said layers having dimensions of approximately 11.43 centimeters in length and approximately 2.5 centimeters in height; a first plurality of surface mount pads within said footprints adapted to mount half of said at least twelve integrated circuits on a first of said plurality of conductive layers, wherein said first of said plurality of conductive layers forms a top signal layer of said printed circuit board; a second plurality of surface mount pads within said footprints adapted to mount half of said at least twelve integrated circuits on a second of said plurality of conductive layers, wherein said second of said plurality of conductive layers forms a bottom signal layer of said printed circuit board; and a plurality of microvias within each of said first and second plurality of surface mount pads, wherein each of said plurality of microvias directly electrically connects either said top signal layer to a first ground layer or said bottom signal layer to a second ground layer.
Claim 21
Dependent Claim
27 words
The printed circuit board of claim 17 , further comprising a plurality of connector pinouts adapted to electrically interconnect the printed circuit board to a host board.
Claim 22
Dependent Claim
17 words
The printed circuit board of claim 18 , wherein the printed circuit board has 80 connector pinouts.
Claim 23
Dependent Claim
17 words
The printed circuit board of claim 18 , wherein the printed circuit board has 72 connector pinouts.
Claim 24
Dependent Claim
23 words
The printed circuit board of claim 17 , wherein the first ground layer is the first conductive layer from the top signal layer.
Claim 25
Dependent Claim
23 words
The printed circuit board of claim 17 , wherein the second ground layer is the first conductive layer from the bottom signal layer.
Claim 26
Dependent Claim
29 words
The printed circuit board of claim 17 , wherein the second plurality of surface mount pads is an approximate mirror image of the first plurality of surface mount pads.
Claim 27
Dependent Claim
20 words
The printed circuit board of claim 23 , further comprising at least one via extending through the printed circuit board.
Claim 28
Dependent Claim
31 words
The printed circuit board of claim 24 , wherein said at least one via extends from a quadrant on said top signal layer to a quadrant on said bottom signal layer.
Claim 29
Dependent Claim
21 words
The printed circuit board of claim 17 , wherein at least one of the integrated circuits is a digital signal processor.
Claim 30
Dependent Claim
23 words
The printed circuit board of claim 17 , wherein at least one of the integrated circuits is a static random access memory circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |