US5685070A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making printed circuit board
Assignee: International Business Machines Corp
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Filing: 1995-01-19
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Granted: 1997-11-11
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Expires: 2015-01-19
Abstract
Abstract A printed circuit board or card for direct chip attachment that includes at least one power core, at least one signal plane that is adjacent to the power core, and plated through holes for electrical connection is provided. In addition, a layer of dielectric material is adjacent the power core and a circuitized conductive layer is adjacent the dielectric material, followed by a layer of photosensitive dielectric material adjacent the conductive layer. Photodeveloped blind vias for subsequent connection to the power core and drilled blind vias for subsequent connection to the signal plane are provided. Also provided is process for fabricating the printed circuit board or card for direct chip attachment.
Inventors
- 👤 Warren Alan Alpaugh
- 👤 Voya Rista Markovich
- 👤 Ajit Kumar Trivedi
- 👤 Richard Stuart Zarr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:55
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/11; H05K1/111; H05K1/112; H05K3/00; H05K3/46; H05K3/4602; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W70/67; H10W70/68; H10W70/685; H10W72/00; H10W90/00; H10W90/401; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09372; H05K2201/09472; H05K2201/095; H05K2201/09509; H05K2201/09518; H05K2201/09536; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10674; H05K2203/00; H05K2203/02; H05K2203/0207; H05K2203/13; H05K2203/1377; H05K2203/1394; H05K2203/15; H05K2203/1581; H05K3/0011; H05K3/0017; H05K3/0023; H05K3/0044; H05K3/0047; H05K3/0094; H05K3/4644; H05K3/4652; H10W70/65; H10W70/654; H10W70/655; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/4913; Y10T29/49144; Y10T29/49155; Y10T29/49165
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
114 words
A process for fabricating a printed circuit board or card for direct chip attachment which comprises: (a) providing a subcomposite which comprises at least one power core and at least one signal plane adjacent to said power core, and plated through holes to electrically connect said at least one power core and said at least one signal plane; (b) providing on said subcomposite a layer of dielectric material adjacent said power core and a conductive layer adjacent said dielectric material etching clearance holes into said conductive layer; then applying a layer of photosensitive dielectric, photodeveloping blind vias for subsequent connection to said power core; drilling blind vias for subsequent connection to said signal plane.
Claim 2
Dependent Claim
114 words
A process for fabricating a printed circuit board or card for direct chip attachment which comprises: (a) providing a subcomposite which comprises at least one power core and at least one signal plane adjacent to said power core, and plated through holes to electrically connect said at least one power core and said at least one signal plane; (b) providing on said subcomposite a layer of dielectric material adjacent said power core and a conductive layer adjacent said dielectric material etching clearance holes into said conductive layer; then applying a layer of photosensitive dielectric, photodeveloping blind vias for subsequent connection to said power core; drilling blind vias for subsequent connection to said signal plane.
Claim 3
Dependent Claim
12 words
The process of claims 1 wherein said subcomposite is 4S3P triplate structure.
Claim 4
Dependent Claim
16 words
The process of claim 1 which further includes plating said blind vias with electrically conductive layer.
Claim 5
Dependent Claim
24 words
The process of claim 3 which comprises providing solder on said blind vias and attaching at least one integrated circuit chip to said solder.
Claim 6
Dependent Claim
31 words
The process of claim 1 wherein the photodeveloped blind vias are about 0.5 to about 1.5 mils deep and the drilled blind vias are about 6 to about 14 mils deep.
Claim 7
Dependent Claim
45 words
The process of claim 3 which further comprises directly joining at least one integrated circuit chip to said board or card and wherein said at least one integrated circuit chip is electrically connected to a signal plane and power core of said board or card.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-10 | 2001-05-12 | 2001-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-10 | 2005-05-12 | 2005-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-10 | 2009-05-12 | 2009-11-11 | $7700.00 | Window Closed / Lapsed |