US5665650A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a high density electronic circuit assembly
Assignee: International Business Machines Corp
•
Filing: 1996-05-30
•
Granted: 1997-09-09
•
Expires: 2016-05-30
Abstract
Abstract Photoimageable dielectric materials are coated on substrates, selectively exposed and developed, whereby small vias and interconnection openings are formed between adjacently spaced circuit layers. A conductive paste may be used to provide sequential layer interconnection and surface planarization. No adhesives are required in the manufacture of a circuit assembly having multiple circuit and dielectric layers, and the manufacturing method avoids the requirement for drilled through holes and blind vias.
Inventors
- 👤 John Matthew Lauffer
- 👤 Donald Herman Glatzel
- 👤 David John Russell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:57
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H05; H05K; H05K1/00; H05K1/02; H05K1/11; H05K1/111; H05K1/112; H05K1/113; H05K3/00; H05K3/0011; H05K3/0017; H05K3/0023; H05K3/46; H05K3/4644; H05K3/4652; H05K3/4661; H10W70/60; H10W70/67; H10W70/69; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0335; H05K2201/0355; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09509; H05K2201/0959; H05K2203/00; H05K2203/11; H05K2203/1152; H05K3/0094; H05K3/22; H05K3/28; H05K3/40; H05K3/4038; H05K3/4053; H05K3/4069
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
339 words
A method for manufacturing a high density electronic circuit assembly, comprising: coating at least one planar surface of a substrate member with a photoimageable dielectric material; exposing one or more portions of said photoimageable dielectric material coating to light, thereby forming defined exposed and unexposed areas of the photoimageable dielectric material coating on the surface of the substrate; developing said coated surface of the substrate and thereby removing the unexposed photoimageable dielectric material from the surface of the substrate and forming defined open surface areas on the substrate; partially curing the remaining exposed photoimageable dielectric material on the surface of the substrate; laminating a layer of an electrically conductive material with said dielectric material and said substrate member, said dielectric material being disposed between said layer of electrically conductive material and said substrate and said laminating being carried out at a temperature and for a length of time sufficient to complete the curing of said dielectric material; selectively etching said electrically conductive material and forming at least one first defined electrical circuit disposed on said dielectric material, applying an additional coating of a photoimageable dielectric material on said first defined electrical circuit and said cured dielectric material; exposing one or more portions of said additional coating of photoimageable dielectric material to light, thereby forming defined exposed and unexposed areas of photoimageable dielectric material wherein at least a portion of said unexposed areas are selectively aligned with one or more selected portions of the first electrical circuit and selected ones of the open areas on said substrate; developing said additional coating of photoimageable dielectric material and thereby removing the unexposed photoimageable dielectric material from the additional coating; curing the remaining exposed photoimageable dielectric material on the additional coating and thereby forming a selectively disposed second layer of dielectric material; selectively forming at least one additional electrical circuit, said additional electrical circuit being disposed on said additional layer of dielectric material, selected portions of the first defined electrical circuit, and selected ones of the open surface areas on said substrate member.
Claim 2
Independent Claim
339 words
A method for manufacturing a high density electronic circuit assembly, comprising: coating at least one planar surface of a substrate member with a photoimageable dielectric material; exposing one or more portions of said photoimageable dielectric material coating to light, thereby forming defined exposed and unexposed areas of the photoimageable dielectric material coating on the surface of the substrate; developing said coated surface of the substrate and thereby removing the unexposed photoimageable dielectric material from the surface of the substrate and forming defined open surface areas on the substrate; partially curing the remaining exposed photoimageable dielectric material on the surface of the substrate; laminating a layer of an electrically conductive material with said dielectric material and said substrate member, said dielectric material being disposed between said layer of electrically conductive material and said substrate and said laminating being carried out at a temperature and for a length of time sufficient to complete the curing of said dielectric material; selectively etching said electrically conductive material and forming at least one first defined electrical circuit disposed on said dielectric material, applying an additional coating of a photoimageable dielectric material on said first defined electrical circuit and said cured dielectric material; exposing one or more portions of said additional coating of photoimageable dielectric material to light, thereby forming defined exposed and unexposed areas of photoimageable dielectric material wherein at least a portion of said unexposed areas are selectively aligned with one or more selected portions of the first electrical circuit and selected ones of the open areas on said substrate; developing said additional coating of photoimageable dielectric material and thereby removing the unexposed photoimageable dielectric material from the additional coating; curing the remaining exposed photoimageable dielectric material on the additional coating and thereby forming a selectively disposed second layer of dielectric material; selectively forming at least one additional electrical circuit, said additional electrical circuit being disposed on said additional layer of dielectric material, selected portions of the first defined electrical circuit, and selected ones of the open surface areas on said substrate member.
Claim 3
Dependent Claim
66 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 1, wherein the coating of at least one planar surface of a substrate member includes coating two planar surfaces that are respectively disposed on opposed surfaces of the substrate member, and the subsequent steps of the method are carded out simultaneously on both of said opposed surfaces of the substrate member.
Claim 4
Dependent Claim
66 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 1, wherein selectively forming at least one additional electrical circuit includes: attaching an additional layer of electrically conductive material over said additional layer of dielectric material; and selectively etching said additional layer of electrically conductive material and thereby removing one or more portions of said additional layer of electrically conductive material.
Claim 5
Dependent Claim
80 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 3, wherein said attaching an additional layer of electrically conductive material includes: roughening the additional layer of dielectric material and forming a roughened surface thereon; and plating a layer of an electrically conductive material on said toughened surface of the additional layer of dielectric material, one or more selected portions of the first defined electrical circuit, and the open surface areas on said substrate member.
Claim 6
Dependent Claim
42 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 3, wherein said attaching an additional layer of electrically conductive material includes laminating a layer of an electrically conductive material on said additional layer of dielectric material.
Claim 7
Dependent Claim
60 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 1, wherein subsequent to selectively forming at least one additional electrical circuit, said method includes applying a coating of a solder-resistant dielectric material to selected portions of said additional electrical circuit, said first defined electrical circuit and said open surface areas on said substrate member.
Claim 8
Dependent Claim
192 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 1, wherein after selectively etching said electrically conductive material and forming at least one first defined electrical circuit, said method includes repeating the coating of a photoimageable dielectric material on a previously formed electrical circuit and cured dielectric material, exposing one or more portions of the applied coating of photoimageable dielectric material to light thereby forming defined exposed and unexposed areas of photoimageable dielectric material, developing said applied coating of photoimageable dielectric material and thereby removing the dielectric material from the defined unexposed areas, partially curing the remaining exposed dielectric material and thereby forming a layer of partially cured dielectric material over selected portions of the previously formed electrical circuit and the cured dielectric material, laminating a layer of an electrically conductive material with said partially cured dielectric material at a temperature and for a length of time sufficient to complete the curing of said partially cured dielectric material, and selectively etching the most recently laminated layer of electrically conductive material, until said high density electronic circuit assembly has one or more electrical circuit layers formed therein.
Claim 9
Dependent Claim
94 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 7, wherein said defined unexposed areas of photoimageable dielectric material formed during said exposing one or more portions of the applied coating of photoimageable dielectric material to light includes preselected sites for interconnection vias between a previously formed electrical circuit and a subsequently formed electrical circuit, and after developing said applied coating and removing the dielectric material from the defined unexposed areas said method includes filling said areas from which dielectric material was removed with an electrically conductive paste.
Claim 10
Dependent Claim
66 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 7, wherein the coating of at least one planar surface of a substrate member includes coating two planar surfaces that are respectively disposed on opposed surfaces of the substrate member, and the subsequent steps of the method are carried out simultaneously on both of said opposed surfaces of the substrate member.
Claim 11
Dependent Claim
66 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 7, wherein selectively forming at least one additional electrical circuit includes: attaching an additional layer of electrically conductive material over said additional layer of dielectric material; and selectively etching said additional layer of electrically conductive material and thereby removing one or more portions of said additional layer of electrically conductive material.
Claim 12
Dependent Claim
80 words
A method for manufacturing a high density printed circuit assembly, as set forth in claim 7, wherein said attaching an additional layer of electrically conductive material includes: roughening the additional layer of dielectric material and forming a roughened surface thereon; and plating a layer of an electrically conductive material on said toughened surface of the additional layer of dielectric material, one or more selected portions of the first defined electrical circuit, and the open surface areas on said substrate member.
Claim 13
Dependent Claim
293 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 1, wherein said selectively forming at least one additional electrical circuit includes forming an electrical circuit having at least one site defined thereon for connection with a semiconductor chip, said method further comprising: coating the surface of the electronic circuit assembly, formed according the preceding method and having said defined connection site thereon, with a photoimageable dielectric material; masking selected portions of the coating which overlay said defined connection site; exposing the coating to a source of light whereby unmasked portions of the coating are exposed to the light and masked portions of the coating are unexposed to the light; developing said coating and thereby removing the unexposed portions of the coating whereat defined voids are formed in said coating at said defined connection site; filling said defined voids with an electrically conductive paste; laminating a layer of an electrically conductive material over said dielectric material and said electrically conductive paste, said laminating being carried out at a temperature and for a length of time sufficient to cure said dielectric material and said electrically conductive paste; forming at least one electrical circuit by selectively etching the laminated layer of electrically conductive material, said electrical circuit having a planar surface land adapted for the direct connection of a semiconductor chip thereon and aligned with the defined connection site on the previously formed underlying electrical circuit; applying a coating of a solder-resistant dielectric material to selected portions of said electrical circuit having said planar surface land, said planar surface land not being included in said selected portions and not being coated by said solder-resistant dielectric material; and conditioning said planar surface land for the direct attachment of a semiconductor chip.
Claim 14
Dependent Claim
86 words
A method for manufacturing a high density electronic circuit assembly, as set forth in claim 12, wherein said filling said defined voids with an electrically conductive paste includes filling said defined voids with said paste containing a liquid solvent, and said method subsequently includes: placing the thus formed electronic circuit assembly in an oven; and drying said conductive paste at a temperature and for a length of time sufficient to vaporize the liquid solvent and at least partially cure said conductive paste and said dielectric material.
Claim 15
Independent Claim
265 words
A method for forming a semiconductor chip attachment site on a previously formed electronic circuit board having at least one site defined thereon for the attachment of a semiconductor chip, comprising: coating the surface of the circuit board having the site defined thereon with a photoimage, able dielectric material; masking the portion of the photoimageable dielectric material coating which overlays said defined site; exposing the coating to a source of light whereby unmasked portions of the coating are exposed to the light and masked portions of the coating are unexposed to the light; developing said coating and thereby removing the unexposed portions of the coating wherein a void are formed in said coating at said defined site; filling said void with an electrically conductive paste; laminating a layer of an electrically conductive material over said dielectric material and said electrically conductive paste, said laminating being carried out at a temperature and for a length of time sufficient to cure said dielectric material and said electrically conductive paste; forming at least one electrical circuit by selectively etching the laminated layer of electrically conductive material, said electrical circuit having a planar surface land adapted for the direct connection of a semiconductor chip and aligned with the defined site on the underlying electrical circuit; applying a coating of a solder-resistant dielectric material to selected portions of said electrical circuit having said planar surface land, said planar surface land not being included in said selected portions and not being coated by said solder-resistant dielectric material; and conditioning said planar surface land for the direct attachment of a semiconductor chip.
Claim 16
Independent Claim
265 words
A method for forming a semiconductor chip attachment site on a previously formed electronic circuit board having at least one site defined thereon for the attachment of a semiconductor chip, comprising: coating the surface of the circuit board having the site defined thereon with a photoimage, able dielectric material; masking the portion of the photoimageable dielectric material coating which overlays said defined site; exposing the coating to a source of light whereby unmasked portions of the coating are exposed to the light and masked portions of the coating are unexposed to the light; developing said coating and thereby removing the unexposed portions of the coating wherein a void are formed in said coating at said defined site; filling said void with an electrically conductive paste; laminating a layer of an electrically conductive material over said dielectric material and said electrically conductive paste, said laminating being carried out at a temperature and for a length of time sufficient to cure said dielectric material and said electrically conductive paste; forming at least one electrical circuit by selectively etching the laminated layer of electrically conductive material, said electrical circuit having a planar surface land adapted for the direct connection of a semiconductor chip and aligned with the defined site on the underlying electrical circuit; applying a coating of a solder-resistant dielectric material to selected portions of said electrical circuit having said planar surface land, said planar surface land not being included in said selected portions and not being coated by said solder-resistant dielectric material; and conditioning said planar surface land for the direct attachment of a semiconductor chip.
Claim 17
Dependent Claim
80 words
A method for forming a semiconductor chip attachment site, as set forth in claim 14, wherein said filling said void with an electrically conductive paste includes filling said void with a paste containing a liquid solvent, and said method subsequently includes: placing the coated circuit board in an oven; drying said conductive paste at a temperature and for a length of time sufficient to vaporize the liquid solvent and at least partially cure said conductive paste and said dielectric material.
References Cited (Backward Citations)
US4420364A
Cited
US4893404A
Cited
JPH0245998A
Cited
US4991060A
Cited
US5078831A
Cited
US5079065A
Cited
US5260518A
Cited
US5317801A
Cited
US5065227A
Cited
US5220723A
Cited
US5234536A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-08 | 2001-03-10 | 2001-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-08 | 2005-03-10 | 2005-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-08 | 2009-03-10 | 2009-09-09 | $7700.00 | Window Closed / Lapsed |