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US6163060A
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Semiconductor device with a composite gate dielectric layer and gate barrier layer and method of making same
Assignee: Advanced Micro Devices Inc
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Filing: 1998-09-30
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Granted: 2000-12-19
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Expires: 2018-09-30
Abstract
Abstract The present invention is directed to a new semiconductor device and a method for making same. The new semiconductor device is comprised of a gate barrier layer, a composite gate dielectric layer, a conductor layer, and at least one source/drain region formed in aemiconducting substrate. The method comprises forming the gate barrier layer, composite gate dielectric layer and conductor layer, patterning those layers, and forming at least one source/drain region in said semiconductor substrate. The composite gate dielectric layer is comprised of at least two different materials having different dielectric constants.
Inventors
- 👤 Mark I. Gardner
- 👤 Mark C. Gilmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:12
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D64/01344; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D64/693
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
114 words
A semiconductor device, comprising: a substrate, said substrate having a surface; a gate barrier layer positioned above said surface of said substrate; a composite gate dielectric layer positioned directly on said gate barrier layer, said composite gate dielectric layer comprising at least two different materials having different dielectric constants, wherein at least one of the different dielectric constants is greater than 8, said composite gate dielectric layer having a dielectric constant ranging from approximately 400-800; a conductor layer positioned above said composite gate dielectric layer; a plurality of sidewall spacers formed adjacent at least said gate barrier layer and said composite gate dielectric layer; and at least one source/drain region formed in said substrate.
Claim 2
Dependent Claim
114 words
A semiconductor device, comprising: a substrate, said substrate having a surface; a gate barrier layer positioned above said surface of said substrate; a composite gate dielectric layer positioned directly on said gate barrier layer, said composite gate dielectric layer comprising at least two different materials having different dielectric constants, wherein at least one of the different dielectric constants is greater than 8, said composite gate dielectric layer having a dielectric constant ranging from approximately 400-800; a conductor layer positioned above said composite gate dielectric layer; a plurality of sidewall spacers formed adjacent at least said gate barrier layer and said composite gate dielectric layer; and at least one source/drain region formed in said substrate.
Claim 3
Dependent Claim
23 words
The semiconductor device of claim 1, wherein said gate barrier layer is selected from one of the group of silicon nitride or diamond.
Claim 4
Dependent Claim
20 words
The semiconductor device of claim 1, wherein said composite gate dielectric layer has a thickness range of approximately 1500-1800 Å.
Claim 5
Dependent Claim
19 words
The semiconductor device of claim 1, wherein said composite gate dielectric layer has a dielectric constant between approximately 400-800.
Claim 6
Dependent Claim
23 words
The semiconductor device of claim 1, wherein said composite gate dielectric layer is comprised of barium titanate and silicon dioxide or tetraethyl orthosilicate.
Claim 7
Dependent Claim
18 words
The semiconductor device of claim 1, wherein said gate barrier layer is comprised of silicon nitride or diamond.
Claim 8
Dependent Claim
19 words
The semiconductor device of claim 1, wherein said composite gate dielectric layer has a dielectric constant between approximately 400-800.
Claim 9
Dependent Claim
23 words
The semiconductor device of claim 1, wherein said composite gate dielectric layer is comprised of barium titanate and silicon dioxide or tetraethyl orthosilicate.
Claim 10
Dependent Claim
21 words
The semiconductor device of claim 1, wherein said composite gate dielectric layer may have a thickness range of approximately 1500-1800 Å.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-19 | 2004-06-19 | 2004-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-19 | 2008-06-19 | 2008-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-19 | 2012-06-19 | 2012-12-19 | $7700.00 | Window Closed / Lapsed |