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US5789778A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device with gate insulator film

Assignee: UMC Japan Co Ltd
•
Filing: 1996-10-07
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Granted: 1998-08-04
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Expires: 2016-10-07
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Abstract

Abstract A gate electrode comprises a conductive gate electrode body and gate side walls. The channel region beneath the gate electrode has an NUDC structure having a p - impurity region and p + impurity regions. The p - impurity region is formed before the gate electrode body. After the formation of the gate electrode body, the p + impurity regions are formed by ion implantation before the gate side walls. The ion implantation is carried out perpendicular to the substrate so that the implanted ions will not reach further around the center of the channel region. Of the gate oxide films over the channel region, the thickness of the gate oxide films at both ends of the channel region is thinner than that of the gate oxide film in the middle of the channel length so as to suppress lowering of the current drivability.

Inventors

  • 👤 Ichiro Murai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 10:57
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01346; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D64/01304; H10D64/01322; H10D64/01324; H10D64/0134; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 78 words
A semiconductor device which is a MOS device with a gate electrode on a semiconductor substrate via a gate insulator film, comprising: a channel region wherein the impurity concentration in a middle region thereof is low in the direction of the carrier movement while that of both ends thereof is high; and the middle of said gate insulator film is thick in the direction of the carrier movement while both ends of said gate insulator film are thin.
Claim 2
Dependent Claim 78 words
A semiconductor device which is a MOS device with a gate electrode on a semiconductor substrate via a gate insulator film, comprising: a channel region wherein the impurity concentration in a middle region thereof is low in the direction of the carrier movement while that of both ends thereof is high; and the middle of said gate insulator film is thick in the direction of the carrier movement while both ends of said gate insulator film are thin.
Claim 3
Dependent Claim 103 words
A semiconductor device which is a MOS device with a gate electrode on a semiconductor substrate via a gate insulator film, comprising: a channel region wherein the impurity concentration in a middle region thereof is low in the direction of the carrier movement while that of both ends thereof is high, wherein the middle of said gate insulator film is thick in the direction of the carrier movement while both ends of said gate insulator film are thin; and said gate electrode has a conductive gate electrode body and conductive gate side walls separately formed at the sides of said gate electrode body.
Claim 4
Dependent Claim 103 words
A semiconductor device which is a MOS device with a gate electrode on a semiconductor substrate via a gate insulator film, comprising: a channel region wherein the impurity concentration in a middle region thereof is low in the direction of the carrier movement while that of both ends thereof is high, wherein the middle of said gate insulator film is thick in the direction of the carrier movement while both ends of said gate insulator film are thin; and said gate electrode has a conductive gate electrode body and conductive gate side walls separately formed at the sides of said gate electrode body.
Claim 5
Dependent Claim 59 words
A semiconductor device according to claim 2 wherein: the channel region comprises high concentration regions formed beneath said gate side walls and a low concentration region formed beneath said gate electrode body; and thicknesses of said gate insulator film in the high concentration regions are thinner than a thickness of said gate insulator film in the low concentration region.

References Cited (Backward Citations)

JPS61256670A Cited
US5266823A Cited
US5422505A Cited
US5512771A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-08-03 2002-02-02 2002-08-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-08-03 2006-02-02 2006-08-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-08-03 2010-02-02 2010-08-04 $7700.00 Window Closed / Lapsed

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