US6015739A
Expired / Lapsed
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Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant
Assignee: Lone Star Silicon Innovations LLC
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Filing: 1997-10-29
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Granted: 2000-01-18
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Expires: 2017-10-29
Abstract
Abstract A process for fabricating a gate dielectric stack of a MOS transistor. A native oxide film is formed on an upper surface of a semiconductor substrate. A silicon nitride layer is then deposited on the native oxide film. A final dielectric film is then formed on the silicon nitride film. A dielectric constant of the final dielectric film is in the range of approximately 20-200. The substrate is then annealed in an inert ambient to produce the gate dielectric stack. An equivalent silicon dioxide thickness of the dielectric stack is typically in the range of approximately 5-20 angstroms whereby a gate dielectric stack suitable for use in deep sub-micron transistor is fabricated with a film thickness substantially in excess of an electrically equivalent silicon dioxide film. A suitable material for the final dielectric film includes oxides comprising oxygen and an element such as beryllium, magnesium, calcium, zirconium, titanium, or tantalum.
Inventors
- 👤 Mark I. Gardner
- 👤 H. Jim Fulford
- 👤 Dim-Lee Kwong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:19
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01342; H10D64/01344; H10D64/01352; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D64/693; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
94 words
A process for fabricating a gate dielectric stack of an MOS transistor, said process comprising: forming a native oxide film on an upper surface of a semiconductor substrate; depositing a silicon nitride layer on said native oxide film; forming a final dielectric film on said silicon nitride film, wherein a dielectric constant of said final dielectric film is in the range of approximately 20 to 200; and annealing said semiconductor substrate in an inert ambient, whereby said native oxide film, said silicon nitride layer, and said final dielectric film comprise said gate dielectric stack.
Claim 2
Dependent Claim
94 words
A process for fabricating a gate dielectric stack of an MOS transistor, said process comprising: forming a native oxide film on an upper surface of a semiconductor substrate; depositing a silicon nitride layer on said native oxide film; forming a final dielectric film on said silicon nitride film, wherein a dielectric constant of said final dielectric film is in the range of approximately 20 to 200; and annealing said semiconductor substrate in an inert ambient, whereby said native oxide film, said silicon nitride layer, and said final dielectric film comprise said gate dielectric stack.
Claim 3
Dependent Claim
50 words
The process of claim 1, wherein the step of forming said native oxide film comprises exposing said semiconductor substrate to an oxygen bearing ambient maintained at a temperature in the range of approximately 15 to 200° C. for a duration in the range of approximately 10 seconds to 20 minutes.
Claim 4
Dependent Claim
37 words
The process of claim 2, wherein a thickness of said native oxide film is approximately 5 angstroms and further wherein a dielectric constant of said native oxide film is in the range of approximately 3.9 to 4.2.
Claim 5
Dependent Claim
46 words
The process of claim 1, wherein the step of depositing said silicon nitride film comprises decomposing silane and ammonium in a CVD reactor chamber maintained at a temperature in the range of approximately 200 to 800° C. and a pressure of less than approximately 2 torrs.
Claim 6
Dependent Claim
63 words
The process of claim 1, wherein a thickness of said silicon nitride film is in the range of approximately 10 to 20 angstroms and further wherein a dielectric constant of said silicon nitride film is in the range of approximately 8 to 9, whereby an equivalent oxide thickness of said silicon nitride film is in the range of approximately 5 to 10 angstroms.
Claim 7
Dependent Claim
37 words
The process of claim 1, wherein the step of forming said final dielectric film comprises depositing a dielectric material comprised of oxygen and a material selected from the group comprising Be, Mg, Ca, Zr, Ti, and Ta.
Claim 8
Dependent Claim
43 words
The process of claim 1, wherein a thickness of said final dielectric film is in the range of approximately 20 to 500 angstroms and wherein an equivalent oxide thickness of said dielectric film is in the range of approximately 5 to 10 angstroms.
Claim 9
Dependent Claim
44 words
The process of claim 1, wherein the step of annealing comprises immersing said semiconductor substrate in an inert ambient maintained at a temperature in the range of approximately 600 to 1100° C. for a duration in the range of approximately 2 to 20 minutes.
Claim 10
Dependent Claim
121 words
A process for forming a graded dielectric stack for use as a gate dielectric film of an MOS transistor, said process comprising: forming a first dielectric film on an upper surface of a semiconductor substrate, said first dielectric film comprising a first thickness and a first dielectric constant; forming a second dielectric film on said first dielectric film, said second dielectric film comprising a second dielectric constant and a second thickness; forming a third dielectric film on an upper surface of said second dielectric film, wherein said third dielectric film comprises a third thickness and a third dielectric constant; and annealing said semiconductor substrate in an inert ambient maintained at a temperature in the range of approximately 600 to 1100° C.
Claim 11
Dependent Claim
121 words
A process for forming a graded dielectric stack for use as a gate dielectric film of an MOS transistor, said process comprising: forming a first dielectric film on an upper surface of a semiconductor substrate, said first dielectric film comprising a first thickness and a first dielectric constant; forming a second dielectric film on said first dielectric film, said second dielectric film comprising a second dielectric constant and a second thickness; forming a third dielectric film on an upper surface of said second dielectric film, wherein said third dielectric film comprises a third thickness and a third dielectric constant; and annealing said semiconductor substrate in an inert ambient maintained at a temperature in the range of approximately 600 to 1100° C.
Claim 12
Dependent Claim
49 words
The process of claim 9, wherein said second thickness and said second dielectric constant are greater than said first thickness and said first dielectric constant respectively, and further wherein said third thickness and said third dielectric constant are greater than said second thickness and said second dielectric constant respectively.
Claim 13
Dependent Claim
28 words
The process of claim 9, wherein equivalent oxide thicknesses of said first, second, and third dielectric films are all in the range of approximately 5 to 15 angstroms.
Claim 14
Dependent Claim
21 words
The process of claim 9, wherein said first dielectric comprises silicon dioxide and wherein said first thickness is approximately 5 angstroms.
Claim 15
Dependent Claim
15 words
The process of claim 9, wherein said second dielectric film comprises a nitrogen bearing species.
Claim 16
Dependent Claim
33 words
The process of claim 13, wherein said second dielectric film comprises silicon nitride and further wherein a thickness of said second dielectric film is in the range of approximately 10 to 20 angstroms.
Claim 17
Dependent Claim
34 words
The process of claim 9, wherein said third dielectric constant is in the range of approximately 20 to 200 and further said third thickness is in the range of approximately 25 to 250 angstroms.
Claim 18
Dependent Claim
27 words
The process of claim 9, wherein said third dielectric film comprises oxygen and an element selected from the group comprising Be, Mg, Ca, Ti, Zr, and Ta.
Claim 19
Dependent Claim
92 words
The process of claim 9, further comprising: forming a conductive gate layer on an upper surface of said gate dielectric stack, wherein a sheet resistivity of said conductive gate layer is less than approximately 50 Ω/square; patterning said conductive gate layer to form a conductive gate electrode, wherein said conductive gate electrode is aligned over a channel region of said semiconductor substrate; and implanting a source/drain impurity distribution comprising boron, phosphorous, or arsenic into a pair of source/drain regions laterally displaced within said semiconductor substrate on either side of said channel region.
References Cited (Backward Citations)
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