Method of fabricating an ion sensitive field effect transistor with a Ta2 O5 hydrogen ion sensing membrane

Claim 3

The method according to claim 1, wherein said film of Ta 2 O 5 is deposited by RF reactive sputtering.

Claim 4

The method according to claim 1, wherein said film of Ta 2 O 5 formed in the areas surrounding said gate region of said ion sensitive field effect transistor are removed by a lift-off process utilizing a positive photosensitive film during a formation of said film of Ta 2 O 5 on said ion sensitive field effect transistor with said Si 3 N 4 /SiO 2 gate dielectric layer.

Claim 5

An ion sensitive field-effect transistor, comprising: a semiconductor substrate of a first conductivity type having first and second diffusion regions of a second conductivity type separated and spaced-apart by a gate region, said first and second diffusion regions respectively defining a source region and a drain region; a dielectric layer positioned upon the surface of said semiconductor substrate covering said source region, said gate region and said drain region; an ion sensitive membrane formed on the dielectric layer over said gate region, said ion sensitive membrane being a Ta 2 O 5 compound having a thickness of approximately 400-500 Å; and first and second metal layers formed in V-shape and positioned upon the dielectric layer over said source region and said drain region, each of said first and second metal layers having a base at a center of one of said source region and said drain region.

Claim 6

An ion sensitive field-effect transistor, comprising: a semiconductor substrate of a first conductivity type having first and second diffusion regions of a second conductivity type separated and spaced-apart by a gate region, said first and second diffusion regions respectively defining a source region and a drain region; a dielectric layer positioned upon the surface of said semiconductor substrate covering said source region, said gate region and said drain region; an ion sensitive membrane formed on the dielectric layer over said gate region, said ion sensitive membrane being a Ta 2 O 5 compound having a thickness of approximately 400-500 Å; and first and second metal layers formed in V-shape and positioned upon the dielectric layer over said source region and said drain region, each of said first and second metal layers having a base at a center of one of said source region and said drain region.

Claim 7

The ion sensitive field-effect transistors as claimed in claim 4, wherein said ion sensitive membrane is formed on the dielectric layer by RF reactive sputtering and annealing at a temperature in the range of 300° to 900° C. in a reactive oxygen gas ambience for approximately one hour.

Claim 8

The ion sensitive field-effect transistor as claimed in claim 5, wherein the range of temperature of the annealing is prefer to be of 375° to 425° C. in a reactive oxygen gas ambience for approximately one hour.

Claim 9

The ion sensitive field-effect transistor as claimed in claim 4, wherein said ion sensitive membrane is formed on the dielectric layer by RF reactive sputtering and annealing at a temperature in the range of 375° to 400° C. in a reactive oxygen gas ambience for approximately one hour.

Claim 10

The method according to claim 1, wherein the temperature of the annealing of approximately 400° in a reactive oxygen gas ambience for approximately one hour.

Claim 11

The ion sensitive field-effect transistor as claimed in claim 4, wherein the temperature of the annealing is preferred to be of approximately 400° C. in a reactive oxygen gas ambience for approximately one hour.

Claim 14

The method of fabricating an ion sensitive field effect transistor as claimed in claim 10, wherein said reactive gas ambience is oxygen.

Claim 15

The method of fabricating an ion sensitive field effect transistor as claimed in claim 10, wherein said ion sensitive layer is deposited by RF reactive sputtering.

Claim 16

The method of fabricating an ion sensitive field effect transistor as claimed in claim 10, wherein said ion sensitive layer is annealed in said reactive gas ambience for approximately one hour.

Claim 17

The method of fabricating an ion sensitive field effect transistor as claimed in claim 10, wherein the temperature of the annealing is approximately at 400° C. in said reactive gas ambience of oxygen for approximately one hour.

Claim 20

The method of fabricating an ion sensitive field effect transistor as claimed in claim 15, wherein said first gas ambience comprises argon and oxygen and said second gas ambience comprises oxygen, and said film of Ta 2 O 5 is being annealed in said second gas ambience for approximately one hour.

Claim 21

The method of fabricating an ion sensitive field effect transistor as claimed in claim 15, wherein said film of Ta 2 O 5 is being annealed at a temperature range of approximately 375° to 425° C.

Claim 22

The method of fabricating an ion sensitive field effect transistor as claimed in claim 16, wherein said film of Ta 2 O 5 is being annealed at a temperature range of approximately 400° C. in said second gas ambience of oxygen for approximately one hour.

Claim 23

An ion sensitive field effect transistor, comprising: a semiconductor substrate of a first conductivity type having first and second diffusion regions of a second conductivity type separated and spaced-apart by a gate region, each of said first and second diffusion regions respectively defining a source region and a drain region; an insulation layer disposed over the surface of said semiconductor substrate covering said source region, said gate region and said drain region; first and second metal layers positioned upon the insulation layer over said source region and said drain region, each of said first and second metal layers having a base at a center of each of said source and drain regions, and a channel having two ends extending in opposite directions away from the center of each of said source and drain regions; and an ion sensitive layer of Ta 2 O 5 having a thickness of approximately 400-500 Å disposed on the insulation layer over the gate region, wherein said ion sensitive layer being disposed on said insulation layer over the gate region comprises the steps of: depositing a photoresist layer on the surface of said first and second metal layers, thereby exposing said gate region; sputtering said ion sensitive layer of Ta 2 O 5 having a thickness of approximately 400-500 Å over the surface of said photoresist layer and said gate region in a first gas ambience of argon and oxygen; and removing said photoresist layer, thereby exposing said ion sensitive layer of Ta 2 O 5 having a thickness of approximately 400-500 Å over said gate region; and annealing said semiconductor substrate having said ion sensitive layer of Ta 2 O 5 over the gate region in a second gas ambience of oxygen.

Claim 24

An ion sensitive field effect transistor, comprising: a semiconductor substrate of a first conductivity type having first and second diffusion regions of a second conductivity type separated and spaced-apart by a gate region, each of said first and second diffusion regions respectively defining a source region and a drain region; an insulation layer disposed over the surface of said semiconductor substrate covering said source region, said gate region and said drain region; first and second metal layers positioned upon the insulation layer over said source region and said drain region, each of said first and second metal layers having a base at a center of each of said source and drain regions, and a channel having two ends extending in opposite directions away from the center of each of said source and drain regions; and an ion sensitive layer of Ta 2 O 5 having a thickness of approximately 400-500 Å disposed on the insulation layer over the gate region, wherein said ion sensitive layer being disposed on said insulation layer over the gate region comprises the steps of: depositing a photoresist layer on the surface of said first and second metal layers, thereby exposing said gate region; sputtering said ion sensitive layer of Ta 2 O 5 having a thickness of approximately 400-500 Å over the surface of said photoresist layer and said gate region in a first gas ambience of argon and oxygen; and removing said photoresist layer, thereby exposing said ion sensitive layer of Ta 2 O 5 having a thickness of approximately 400-500 Å over said gate region; and annealing said semiconductor substrate having said ion sensitive layer of Ta 2 O 5 over the gate region in a second gas ambience of oxygen.

Claim 25

The ion sensitive field effect transistor as claimed in claim 19, wherein said ion sensitive layer of Ta 2 O 5 is annealed in said second gas ambience for approximately one hour at a temperature range of 375° to 425° C.