US6147857A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Optional on chip power supply bypass capacitor
Assignee: Individual
•
Filing: 1997-10-07
•
Granted: 2000-11-14
•
Expires: 2017-10-07
Abstract
Abstract An integrated circuit includes main power busses located on the next to the top most level of metal and a top level of metal separated from the main power busses by a thin dielectric. The top most level metal is connected to one of the power buses either through bond wires or through contacts. This structure provides a distributed bypass capacitance between the power buses thus stabilizing the power bus voltage within the integrated circuit. Furthermore, this capacitance structure can be optional and can be made with one or two masking steps.
Inventors
- 👤 Eugene Robert Worley
- 👤 Richard Arthur Mann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:26
CPC Classifications
H; H10; H10D; H10D88/00; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W20/495; H10W20/496; H10W72/00; H10W72/90; H10W70/00; H10W70/60; H10W72/071; H10W72/075; H10W72/50; H10W72/531; H10W72/536; H10W72/541; H10W72/547; H10W72/5473; H10W72/59; H10W72/921; H10W72/922; H10W72/931; H10W72/932; H10W72/951; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
189 words
A semiconductor integrated circuit comprising: a semiconductor substrate; circuits formed on said substrate; power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits; an insulating layer formed on said substrate over said power and ground rails; a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor; means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails; said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to a bond pad connected to at least one of said power rails or to at least one of said ground rails.
Claim 2
Dependent Claim
189 words
A semiconductor integrated circuit comprising: a semiconductor substrate; circuits formed on said substrate; power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits; an insulating layer formed on said substrate over said power and ground rails; a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor; means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails; said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to a bond pad connected to at least one of said power rails or to at least one of said ground rails.
Claim 3
Dependent Claim
186 words
A semiconductor integrated circuit comprising: a semiconductor substrate; circuits formed on said substrate; power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits; an insulating layer formed on said substrate over said power and ground rails; a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor; means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails; said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to a bond pad located on a package which connects to a power pin or to a ground pin.
Claim 4
Dependent Claim
186 words
A semiconductor integrated circuit comprising: a semiconductor substrate; circuits formed on said substrate; power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits; an insulating layer formed on said substrate over said power and ground rails; a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor; means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails; said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to a bond pad located on a package which connects to a power pin or to a ground pin.
Claim 5
Dependent Claim
180 words
A semiconductor integrated circuit comprising: a semiconductor substrate connected to a package floor metal plate; circuits formed on said substrate; power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits; an insulating layer formed on said substrate over said power and ground rails; a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor; means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails; said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to said package floor metal plate.
Claim 6
Dependent Claim
180 words
A semiconductor integrated circuit comprising: a semiconductor substrate connected to a package floor metal plate; circuits formed on said substrate; power rails and ground rails formed on said substrate, each of said rails being used to supply power for said circuits and said rails being formed on a top most interconnect metal layer of said circuits; an insulating layer formed on said substrate over said power and ground rails; a metal layer formed on said insulating layer acting as a top capacitor plate with said power and ground rails acting as a lower capacitor plate and said metal layer substantially covering said rails thereby forming a power supply bypass capacitor; means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails; said means for connecting said top capacitor plate to at least one of said power rails or to at least one of said ground rails comprising a bond wire leading from a bond pad connected to said top capacitor plate to said package floor metal plate.
References Cited (Backward Citations)
US4598307A
Cited
US4737830A
Cited
US4937649A
Cited
US4929989A
Cited
US4864464A
Cited
JPH02260559A
Cited
US5200364A
Cited
US5834348A
Cited
US5598029A
Cited
US5652693A
Cited
US5482897A
Cited
US5629240A
Cited
US5780930A
Cited
US5590017A
Cited
US5730835A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-14 | 2004-05-15 | 2004-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-14 | 2008-05-15 | 2008-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-14 | 2012-05-15 | 2012-11-14 | $7700.00 | Window Closed / Lapsed |