US5482897A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with on-chip ground plane
Assignee: Bell Semiconductor LLC
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Filing: 1994-07-19
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Granted: 1996-01-09
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Expires: 2014-07-19
Abstract
Abstract An integrated circuit includes a ground plane structure which provides a uniform ground potential throughout the integrated circuit and improves its performance. The ground plane structure is carried atop the active circuit elements of the integrated circuit and connects with each of the ground-potential contact pads of the circuit. A method of making the integrated circuit includes applying a ground plane precursor structure over all of the integrated circuit topology, and removing portions of the precursor structure where the ground plane is not desired. A method of providing bump structures at each of the contact pads for use in TAB bonding of the electrical connections of the integrated circuit to a package structure is also set forth.
Inventors
- 👤 Brian J. Lynch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W72/00; H10W72/90; H10W70/00; H10W70/60; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/20; H10W72/29; H10W72/50; H10W72/531; H10W72/536; H10W72/59; H10W72/951; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121; Y10T29/49169
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
151 words
A method of making an integrated circuit, said method comprising the steps of: providing an integrated circuit with a substrate having a plurality of fine-dimension integrated circuit elements, a plurality of electrical contact pads, and a passivating layer covering said circuit elements while exposing said contact pads; sputtering a barrier metal layer and then a conductor metal layer over the entire surface of the passivating layer including also onto the exposed contact pads; photolithographically patterning a ground plane structure connecting with selected ones of said contact pads which are ground-potential contact pads; and removing a selected portion of the barrier metal and conductor metal layers where the ground plane structure is not desired; wherein said step of removing a selected portion of the barrier metal and conductor metal layers includes removing a portion of said layers around each one of said plural contact pads which is not a ground-potential contact pad.
Claim 2
Independent Claim
151 words
A method of making an integrated circuit, said method comprising the steps of: providing an integrated circuit with a substrate having a plurality of fine-dimension integrated circuit elements, a plurality of electrical contact pads, and a passivating layer covering said circuit elements while exposing said contact pads; sputtering a barrier metal layer and then a conductor metal layer over the entire surface of the passivating layer including also onto the exposed contact pads; photolithographically patterning a ground plane structure connecting with selected ones of said contact pads which are ground-potential contact pads; and removing a selected portion of the barrier metal and conductor metal layers where the ground plane structure is not desired; wherein said step of removing a selected portion of the barrier metal and conductor metal layers includes removing a portion of said layers around each one of said plural contact pads which is not a ground-potential contact pad.
Claim 3
Dependent Claim
23 words
The method of claim 1 additionally including the step of effecting electrical connection with said integrated circuit individually at said plural contact pads.
Claim 4
Dependent Claim
32 words
The method of claim 2 wherein said step of effecting electrical connection with said contact pads includes the step of connecting wire bond conductors with selected ones of said plural contact pads.
Claim 5
Dependent Claim
66 words
The method of claim 3 additionally including the steps of: photolithographic processing said integrated circuit to add a layer of photoresist over said ground plane structure and contact pads, exposure of said photoresist to light in a pattern corresponding to a positive or negative of said contact pads, and removal of the photoresist layer over the contact pads to define respective openings in said photoresist layer.
Claim 6
Independent Claim
221 words
A method of making an integrated circuit, said method comprising the steps of: providing an integrated circuit with a substrate having a plurality of fine-dimension integrated circuit elements, a plurality of electrical contact pads, and a passivating layer covering said circuit elements while exposing said contact pads; sputtering a barrier metal layer and then a conductor metal layer over the entire surface of the passivating layer including also onto the exposed contact pads; photolithographically patterning a ground plane structure connecting with selected ones of said contact pads which are ground-potential contact pads; and removing a selected portion of the barrier metal and conductor metal layers where the ground plane structure is not desired; effecting electrical connection with said integrated circuit individually at said plural contact pads; photolithographic processing said integrated circuit to add a layer of photoresist over said ground plane structure and contact pads, exposure of said photoresist to light in a pattern corresponding to a positive or negative of said contact pads, and removal of the photoresist layer over the contact pads to define respective openings in said photoresist layer; electroplating conductive metal onto said ground plane structure into said openings of said photoresist layer to build up metallic thickness thereat; and with said thickness of conductive metal in said openings forming respective bump structures on the contact pads.
Claim 7
Independent Claim
221 words
A method of making an integrated circuit, said method comprising the steps of: providing an integrated circuit with a substrate having a plurality of fine-dimension integrated circuit elements, a plurality of electrical contact pads, and a passivating layer covering said circuit elements while exposing said contact pads; sputtering a barrier metal layer and then a conductor metal layer over the entire surface of the passivating layer including also onto the exposed contact pads; photolithographically patterning a ground plane structure connecting with selected ones of said contact pads which are ground-potential contact pads; and removing a selected portion of the barrier metal and conductor metal layers where the ground plane structure is not desired; effecting electrical connection with said integrated circuit individually at said plural contact pads; photolithographic processing said integrated circuit to add a layer of photoresist over said ground plane structure and contact pads, exposure of said photoresist to light in a pattern corresponding to a positive or negative of said contact pads, and removal of the photoresist layer over the contact pads to define respective openings in said photoresist layer; electroplating conductive metal onto said ground plane structure into said openings of said photoresist layer to build up metallic thickness thereat; and with said thickness of conductive metal in said openings forming respective bump structures on the contact pads.
Claim 8
Dependent Claim
37 words
The method of claim 5 wherein said step of building up metallic thickness at said contact pads is effected using as said conductive metal a metal the same as said conductor metal of said ground plane structure.
Claim 9
Dependent Claim
27 words
The method of claim 5 additionally including the step of removing remaining photoresist material from said bump structures at said contact pads which are ground-potential contact pads.
Claim 10
Dependent Claim
14 words
The method of claim 7 further including the step of annealing said bump structures.
Claim 11
Dependent Claim
38 words
The method of claim 8 additionally including the step of effecting electrical connection with said integrated circuit by use of a TAB bonding member electrically connecting with each of said plurality of bump structures on said contact pads.
References Cited (Backward Citations)
US5229642A
Cited
US5202751A
Cited
US5234866A
Cited
US4937649A
Cited
US5072274A
Cited
US4965226A
Cited
US5025299A
Cited
US4933743A
Cited
US5117276A
Cited
US5145800A
Cited
US5158911A
Cited
US5238872A
Cited
US5290731A
Cited
US5221858A
Cited
US5362656A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |