Semiconductor integrated circuit having a capacitor for stabilizing a voltage at a power supplying wiring

Claim 2

A semiconductor integrated circuit comprising: a semiconductor substrate; a plurality of logic gates formed on said semiconductor substrate; a plurality of pairs of power and ground wirings formed on said semiconductor substrate, each of said pairs being provided for each one of said logic gates to supply power thereto; an insulator layer formed on said semiconductor substrate; a capacitor overlying said insulator layer and covering said power and ground wirings through said insulator layer, said capacitor being formed of a lower conductive layer distributed over substantially a whole surface of said semiconductor substrate, a dielectric film layer covering said lower conductive layer and an upper conductive layer formed on said dielectric film layer to cover substantially the whole surface of said semiconductor substrate; first means for connecting said power wirings to one of said lower and upper conductive layers, each of said power wirings being connected to a first connecting portion of said one of said lower and upper conductive layers, which is positioned directly upon respective power wirings; and second means for connecting said ground wirings to the other of said lower and upper conductive layers, each of said ground wirings being connected to a second connecting portion of said other of said lower and upper conductive layers, which is positioned directly upon respective ground wirings, whereby said power and ground wirings are electrically shielded from external noise.

Claim 3

A semiconductor circuit as claimed in claim 1, wherein said insulator layer is an insulation film formed over said power and ground wirings and having holes having said first and second means.

Claim 4

A semiconductor integrated circuit as claimed in claim 1, wherein said lower conductive layer is of a comb-like pattern and has a plurality of teeth to allow said second means to pass through spaces between said teeth.

Claim 5

A semiconductor integrated circuit comprising: a semiconductor substrate; a plurality of logic gates formed on said semiconductor substrate; a plurality of ground wirings formed on said semiconductor substrate via an insulator material to supply a ground potential to said logic gates, each of said ground wirings being provided for each of said logic gates; a plurality of power source wirings formed on said semiconductor substrate via said insulator material to supply a power voltage to said logic gates, each of said power source wirings being provided for each of said logic gates; an insulating film formed on said ground and power source wirings to overlie said wirings, said insulating film having first holes on said ground and power source wirings; a first metal layer formed on said insulating film to cover substantially a whole surface of said semiconductor substrate, said first metal layer having a comb-like pattern and being connected to said power source wiring with a plurality of first connecting means through said first holes on said power source wirings; a dielectric material layer of a dielectric material different from that of said insulator material, formed on said first metal layer, said dielectric material layer having second holes extending from said ground wirings, said second holes being formed so as to be separate from said first metal layer; and a second metal layer formed on said dielectric material layer to cover substantially a whole surface of said semiconductor substrate, said second metal layer being connected to said ground wirings with a plurality of second connecting means through said first holes on said ground wirings and said second holes.

Claim 6

A semiconductor integrated circuit comprising: a semiconductor substrate; a plurality of logic gates formed on said semiconductor substrate; a plurality of ground wirings formed on said semiconductor substrate via an insulator material to supply a ground potential to said logic gates, each of said ground wirings being provided for each of said logic gates; a plurality of power source wirings formed on said semiconductor substrate via said insulator material to supply a power voltage to said logic gates, each of said power source wirings being provided for each of said logic gates; an insulating film formed on said ground and power source wirings to overlie said wirings, said insulating film having first holes on said ground and power source wirings; a first metal layer formed on said insulating film to cover substantially a whole surface of said semiconductor substrate, said first metal layer having a comb-like pattern and being connected to said power source wiring with a plurality of first connecting means through said first holes on said power source wirings; a dielectric material layer of a dielectric material different from that of said insulator material, formed on said first metal layer, said dielectric material layer having second holes extending from said ground wirings, said second holes being formed so as to be separate from said first metal layer; and a second metal layer formed on said dielectric material layer to cover substantially a whole surface of said semiconductor substrate, said second metal layer being connected to said ground wirings with a plurality of second connecting means through said first holes on said ground wirings and said second holes.

Claim 7

A semiconductor integrated circuit as claimed in claim 2, wherein said dielectric film layer is made of tantalum oxide.

Claim 8

A semiconductor integrated circuit comprising: a semiconductor substrate; a plurality of logic gates formed on said semiconductor substrate; a plurality of pairs of power and ground wirings formed on said semiconductor substrate, each of said pairs being provided for each one of said logic gates to supply power thereto; an insulator layer formed on said semiconductor substrate; a capacitor superposed on said insulator layer, said power and ground wirings being surrounded by said insulator layer, said capacitor covering said wirings via said insulator layer and being formed of a lower conductive layer distributed over substantially a whole surface of said semiconductor substrate, a dielectric film layer covering said lower conductive layer, and an upper conductive layer formed on said dielectric film layer to cover substantially the whole surface of said semiconductor substrate; first means for connecting said power wirings to one of said lower and upper conductive layers, each of said power wirings being connected to a first connecting portion of said one of said lower and upper conductive layers, which is positioned directly upon respective wirings; and second means for connecting said ground wirings to the other of said lower and upper conductive layers, each of said ground wirings being connected to a second connecting portion of said other of said lower and upper conductive layers, which is positioned directly upon respective ground wirings.

Claim 9

A semiconductor integrated circuit comprising: a semiconductor substrate; a plurality of logic gates formed on said semiconductor substrate; a plurality of pairs of power and ground wirings formed on said semiconductor substrate, each of said pairs being provided for each one of said logic gates to supply power thereto; an insulator layer formed on said semiconductor substrate; a capacitor superposed on said insulator layer, said power and ground wirings being surrounded by said insulator layer, said capacitor covering said wirings via said insulator layer and being formed of a lower conductive layer distributed over substantially a whole surface of said semiconductor substrate, a dielectric film layer covering said lower conductive layer, and an upper conductive layer formed on said dielectric film layer to cover substantially the whole surface of said semiconductor substrate; first means for connecting said power wirings to one of said lower and upper conductive layers, each of said power wirings being connected to a first connecting portion of said one of said lower and upper conductive layers, which is positioned directly upon respective wirings; and second means for connecting said ground wirings to the other of said lower and upper conductive layers, each of said ground wirings being connected to a second connecting portion of said other of said lower and upper conductive layers, which is positioned directly upon respective ground wirings.

Claim 10

A semiconductor circuit as claimed in claim 6, wherein said insulator layer is an insulation film formed to cover said power and ground wirings and having holes carrying said first and second means.

Claim 11

A semiconductor integrated circuit as claimed in claim 7, wherein said dielectric film layer is made of tantalum oxide.

Claim 12

A semiconductor integrated circuit as claimed in claim 6, wherein said lower conductive layer is of a comb-like pattern and has a plurality of teeth to allow said second means to pass through spaces between said teeth.