Integrated circuit structure having compensating means for self-inductance effects

Claim 1

In an improved integrated circuit structure comprising a semiconductor substrate having a plurality of active devices formed therein with a Vcc current bus and a Vss bus connected to said active devices thereon, the improvement comprising: (a) capacitance means formed beneath at least one of said busses comprising one or more MGS capacitors having a gate electrode forming a first plate of said capacitance means and electrically connected to one of said busses by at least one conductive path between said first plate and said one of said busses; (b) a doped region formed in said substrate beneath said gate electrode comprising the opposite plate of said capacitance means and separated from said gate electrode by gate oxide means formed on said substrate; and (c) electrode means comprising a source/drain in said substrate contiguous with said doped region and electrically connecting said doped region of said MOS capacitor to the other of said busses; whereby inductance voltages induced in said busses during switching will be compensated for by said capacitance means electrically connected directly between said busses and distributed along said busses to thereby reduce the voltage spikes produced by said induced voltages.