US6143582A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density electronic circuit modules
Assignee: Kopin Corp
•
Filing: 1999-02-12
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Granted: 2000-11-07
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Expires: 2019-02-12
Abstract
Abstract The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.
Inventors
- 👤 Duy-Phach Vu
- 👤 Brenda Dingle
- 👤 Ngwe Cheong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:01
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0214; A; A61; A61B; A61B3/00; A61B3/10; A61B3/113; G; G02; G02B; G02B27/00; G02B27/0093; G02B27/01; G02B27/017; G02B27/0172; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1335; G02F1/133526; G02F1/1345; G02F1/13454; G02F1/136; G02F1/1362; G02F1/136209; G02F1/136277; G09; G09G; G09G3/00; G09G3/20; G09G3/22; G09G3/30; G09G3/34; G09G3/36; H04; H04N; H04N5/00; H04N5/74; H04N5/7416; H04N5/7441; H04N9/00; H04N9/12; H04N9/31; H04N9/3141; H05; H05B; H05B33/00; H05B33/12; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10D30/6758; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D86/40; H10D86/60; H10D88/00; H10D88/01; H10H; H10H29/00; H10H29/10; H10H29/14; H10H29/142; H10W; H10W72/00; H10W72/01; H10W72/0198; H10W90/00; G02B27/0101; G02B2027/0132; G02B2027/0138; G02B27/0179; G02B2027/0187; G02B2027/0192; G02B2027/0198; G02B5/00; G02B5/30; G02F1/13336; G02F1/1347; G02F1/13471; G02F1/13473; G02F1/13613; G02F2202/00; G02F2202/10; G02F2202/105; G09G2300/00; G09G2300/02; G09G2300/023; G09G2300/08; G09G2300/0809; G09G2300/0842; G09G2320/00; G09G2320/02; G09G2320/0233; G09G2320/04; G09G2320/041; G09G2320/043; G09G2340/00; G09G2340/04; G09G2340/0464; G09G2370/00; G09G2370/04; G09G2370/042; G09G3/32; G09G3/3607; G09G3/3611; G09G3/3648; H01; H01S; H01S5/00; H01S5/02; H01S5/0206; H01S5/0217; H01S5/40; H01S5/42; H01S5/423; H04N5/66; H04N5/70; H04N5/7475; H04N5/7491; H10D30/674; H10P; H10P72/00; H10P72/70; H10P72/74; H10P72/743; H10P72/7432; H10P72/7434
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
66 words
A method of fabricating a double gate MOSFET device comprising: forming a device region in a layer of silicon material on a first side of an insulating layer; forming a first gate over the device region on the first side of the insulating layer; and forming a second gate on a second side of the insulating layer, the second gate being aligned with the first gate.
Claim 2
Independent Claim
66 words
A method of fabricating a double gate MOSFET device comprising: forming a device region in a layer of silicon material on a first side of an insulating layer; forming a first gate over the device region on the first side of the insulating layer; and forming a second gate on a second side of the insulating layer, the second gate being aligned with the first gate.
Claim 3
Dependent Claim
48 words
The method of claim 1 further comprising the step of doping the silicon layer to produce a source region and a drain region, each of a first conductivity type, such that respective conductivity junctions exist between the source and channel regions and between the drain and channel regions.
Claim 4
Dependent Claim
15 words
The method of claim 2 wherein the conductivity junctions vertically coincide with the first gate.
Claim 5
Dependent Claim
22 words
The method of claim 2 further comprising the step of attaching conductive contacts to the source, drain and first and second gate.
Claim 6
Dependent Claim
15 words
The method of claim 4 further comprising electrically connecting the first and second gate contacts.
Claim 7
Dependent Claim
40 words
The method of claim 1 further comprising the step of: removing part of the insulating layer opposite the first gate to create a channel; and forming a second gate in the channel on the insulating layer opposite the first gate.
Claim 8
Dependent Claim
40 words
The method of claim 1 further comprising the step of: removing a region of the insulating layer to expose a backside region of the silicon layer; and forming a second gate on the exposed backside region of the silicon layer.
Claim 9
Dependent Claim
21 words
The method of claim 7, wherein the step of removing a region of the insulating layer includes etching the insulating layer.
Claim 10
Dependent Claim
23 words
The method of claim 1 further comprising the step of aligning the second gate with the first gate using a photoresist and mask.
Claim 11
Dependent Claim
15 words
The method of claim 1, wherein the silicon layer is a single crystal silicon structure.
Claim 12
Dependent Claim
25 words
The method of claim 1 further comprising the step of forming a plurality of device regions in the silicon layer to form a silicon-on-insulator structure.
Claim 13
Independent Claim
97 words
A method of fabricating an electronic circuit device comprising: forming a device region in a layer of silicon material on a first side of an insulating layer; forming a first gate over the device region; forming a second gate on a second side of the insulating layer, the second gate being aligned with the first gate; forming a plurality of device regions in the layer of silicon; attaching conductive contacts to the source, drain, first gate and second gate in each device region; transferring the device regions onto a common module body; and interconnecting the circuit elements.
Claim 14
Independent Claim
97 words
A method of fabricating an electronic circuit device comprising: forming a device region in a layer of silicon material on a first side of an insulating layer; forming a first gate over the device region; forming a second gate on a second side of the insulating layer, the second gate being aligned with the first gate; forming a plurality of device regions in the layer of silicon; attaching conductive contacts to the source, drain, first gate and second gate in each device region; transferring the device regions onto a common module body; and interconnecting the circuit elements.
Claim 15
Dependent Claim
31 words
The method of claim 12 further comprising the step of attaching the silicon layer to a second substrate with an adhesive before transferring the device regions to the common module body.
Claim 16
Dependent Claim
31 words
The method of claim 12 further comprising the step of attaching the silicon layer to a transparent substrate with an adhesive before transferring the device regions to the common module body.
Claim 17
Dependent Claim
15 words
The method as described in claim 12, wherein the device regions form a CMOS device.
Claim 18
Dependent Claim
22 words
The method of claim 12 further comprising the step of: forming a multi-layer 3 dimensional circuit stack from the interconnected circuit elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-07 | 2004-05-08 | 2004-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-07 | 2008-05-08 | 2008-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-07 | 2012-05-08 | 2012-11-07 | $7700.00 | Window Closed / Lapsed |