US4774205A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic integration of silicon and gallium arsenide devices
Assignee: Massachusetts Institute of Technology
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Filing: 1986-06-13
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Granted: 1988-09-27
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Expires: 2006-06-13
Abstract
Abstract Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO 2 and Si 3 N 4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si 3 N 4 /SiO 2 layers and final metallization is performed to complete the MOSFET fabrication. In an alternative embodiment, Si MOSFETs and aluminum gallium arsenide double heterostructure LEDs are formed in a similar manner.
Inventors
- 👤 Hong K. Choi
- 👤 Bor-Yeu Tsaur
- 👤 George W. Turner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:26
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/08; H10D84/0123; H10D84/0126; H10D84/0158; H10D86/00; H10D86/01; H10D86/03; H10D87/00; H10H; H10H29/00; H10H29/10; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/072; Y10S148/097; Y10S148/149; Y10S438/00; Y10S438/973
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
146 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of: (a) forming Si devices on selected areas of said substrate; (b) forming a protective layer over the Si devices and portions of the remainder of said substrate laterally displaced from the Si devices; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate; (d) forming a layer of said compound semiconductor over at least the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline to the extent deposited elsewhere; (e) removing the compound semiconductor polycrystalline layer to the extent deposited elsewhere; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor; and (g) then forming ohmic contacts on said devices.
Claim 2
Independent Claim
146 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of: (a) forming Si devices on selected areas of said substrate; (b) forming a protective layer over the Si devices and portions of the remainder of said substrate laterally displaced from the Si devices; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate; (d) forming a layer of said compound semiconductor over at least the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline to the extent deposited elsewhere; (e) removing the compound semiconductor polycrystalline layer to the extent deposited elsewhere; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor; and (g) then forming ohmic contacts on said devices.
Claim 3
Dependent Claim
24 words
The method of claim 1 including forming interconnects for the Si devices and compound semiconductor devices and between the Si and compound semiconductor devices.
Claim 4
Dependent Claim
22 words
The method of claim 1 wherein the substrate comprises a single crystal: silicon, or a silicon on sapphire, or a silicon-on-insulator substrate.
Claim 5
Dependent Claim
16 words
The method of claim 1 wherein the protective layer comprises a layer of SiO 2 .
Claim 6
Dependent Claim
20 words
The method of claim 1 wherein the protective layer comprises layers of SiO 2 and Si 3 N 4 .
Claim 7
Dependent Claim
15 words
The method of claim 1 wherein the compound semiconductor is GaAs or an alloy thereof.
Claim 8
Dependent Claim
15 words
The method of claim 6 wherein the gallium arsenide semiconductor device is an optoelectronic device
Claim 9
Dependent Claim
15 words
The method of claim 1 wherein the Si devices are part of an Si circuit.
Claim 10
Dependent Claim
23 words
The method of claim 1 wherein the compound semiconductor devices are transistors from the class comprising MESFETs, bipolar transistors, or modulation doped FETs.
Claim 11
Dependent Claim
22 words
The method of claim 1 wherein the compound semiconductor devices are optoelectronic devices from the class comprising LED, lasers and light detectors.
Claim 12
Dependent Claim
21 words
The method of claim 1 wherein the compound semiconductor devices are part of a circuit consisting of transistors and optoelectronic devices.
Claim 13
Independent Claim
135 words
A method of fabricating semiconductor devices of gallium arsenide and semiconductor devices of silicon on a common Si, SOS, or SOI substrate surface comprising the steps of: (a) forming a heavily doped connection region in said substrate; (b) forming silicon devices on selected regions of said surface adjacent said connection region with a portion of said silicon devices contacting said connection region; (c) forming a protective layer over said devices and adjacent regions of said substrate; (d) forming openings through said protective layer to expose additional regions of the surface of said substrate, said openings exposing at least a portion of said connection region; (e) forming a gallium arsenide buffer layer over the exposed surface regions; (f) forming a gallium arsenide semiconductor device over the buffer layer; and (g) forming ohmic contacts on said devices.
Claim 14
Independent Claim
135 words
A method of fabricating semiconductor devices of gallium arsenide and semiconductor devices of silicon on a common Si, SOS, or SOI substrate surface comprising the steps of: (a) forming a heavily doped connection region in said substrate; (b) forming silicon devices on selected regions of said surface adjacent said connection region with a portion of said silicon devices contacting said connection region; (c) forming a protective layer over said devices and adjacent regions of said substrate; (d) forming openings through said protective layer to expose additional regions of the surface of said substrate, said openings exposing at least a portion of said connection region; (e) forming a gallium arsenide buffer layer over the exposed surface regions; (f) forming a gallium arsenide semiconductor device over the buffer layer; and (g) forming ohmic contacts on said devices.
Claim 15
Dependent Claim
44 words
The method of claim 12 wherein low resistance interconnection between the Si devices and the gallium arsenide devices is made by heavily doping the buffer layer with the same type conductivity as the connection region during the formation of the gallium arsenide buffer layer.
Claim 16
Dependent Claim
16 words
The method of claim 12 wherein the protective layer comprises a layer of SiO 2 .
Claim 17
Dependent Claim
20 words
The method of claim 12 wherein the protective layer comprises layers of SiO 2 and Si 3 N 4 .
Claim 18
Dependent Claim
38 words
The method of claim 1 wherein prior to step (b) heavily doped n+ islands are formed adjacent and in contact with doped regions of said Si devices to form low resistance interconnection paths to said compound semiconductor device.
Claim 19
Dependent Claim
30 words
The method of claim 1 wherein the silicon devices are formed on selected areas of a silicon single crystal wafer which is oriented at an angle off the crystallographic plane.
Claim 20
Dependent Claim
43 words
The method of claim 1 wherein the ohmic contacts for said Si devices and compound semiconductor devices is formed after the compound semiconductor device is formed and the ohmic contacts for the Si devices is formed through openings made in said protective layer.
Claim 21
Dependent Claim
23 words
The method of claim 12 wherein the ohmic contacts for said silicon devices is made after said gallium arsenide semiconductor device is formed.
Claim 22
Dependent Claim
22 words
The method of claim 12 wherein the ohmic contacts for said silicon devices is made through openings formed in said protective layer.
Claim 23
Independent Claim
210 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate with low resistance interconnections between the compound semiconductor devices and the silicon devices comprising the steps of: (a) forming Si devices on selected areas of a planar surface of said substrate having junctions formed of opposite conductivity regions and wherein one of said regions extends laterally along the planar surface of the substrate; (b) forming a protective layer over the Si devices and portions of said substrate surface; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate including at least a portion of said extended region; (d) forming a buffer layer of said compound semiconductor of the same type conductivity as the extended region over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer to the extent deposited elsewhere; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor with said extended region of said Si devices forming said low resistance interconnection to said buffer layer; and (g) forming ohmic contacts on said devices.
Claim 24
Independent Claim
210 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate with low resistance interconnections between the compound semiconductor devices and the silicon devices comprising the steps of: (a) forming Si devices on selected areas of a planar surface of said substrate having junctions formed of opposite conductivity regions and wherein one of said regions extends laterally along the planar surface of the substrate; (b) forming a protective layer over the Si devices and portions of said substrate surface; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate including at least a portion of said extended region; (d) forming a buffer layer of said compound semiconductor of the same type conductivity as the extended region over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer to the extent deposited elsewhere; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor with said extended region of said Si devices forming said low resistance interconnection to said buffer layer; and (g) forming ohmic contacts on said devices.
Claim 25
Independent Claim
154 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of: (a) forming Si devices on selected areas of said substrate wherein said substrate comprises a single crystal wafer oriented at an angle of about 3° off the (100) crystallographic plane toward the (111) plane; (b) forming a protective layer over the Si devices and the remainder of said substrate; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate; (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor; and (g) forming ohmic contacts on said devices.
Claim 26
Independent Claim
154 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of: (a) forming Si devices on selected areas of said substrate wherein said substrate comprises a single crystal wafer oriented at an angle of about 3° off the (100) crystallographic plane toward the (111) plane; (b) forming a protective layer over the Si devices and the remainder of said substrate; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate; (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor; and (g) forming ohmic contacts on said devices.
Claim 27
Dependent Claim
18 words
The method of claim 1 wherein the layer formed in step (d) is formed by molecular beam epitaxy.
Claim 28
Dependent Claim
60 words
The method of claim 23 wherein prior to the molecular beam epitaxy step the layer in step (d) is comprised of GaAs or an alloy thereof and the exposed surface regions are etched to remove any surface contaminants and the structure thus far formed is subjected to a heat treatment sufficient to desorb any oxide found in such surface regions.
Claim 29
Dependent Claim
43 words
The method of claim 24 wherein the molecular beam epitaxy process commences at a relatively low temperature to promote GaAs nucleation and is then raised to about 580° C. for a GaAs Layer or about 700° C. for an allow of GaAs layer.
Claim 30
Independent Claim
136 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of: (a) forming Si devices on selected areas of said substrate; (b) forming a protective layer over the Si devices and portions of the remainder of said subsrate laterally displaced therefrom; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate; (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor; and (g) then forming ohmic contacts on said devices.
Claim 31
Independent Claim
136 words
A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of: (a) forming Si devices on selected areas of said substrate; (b) forming a protective layer over the Si devices and portions of the remainder of said subsrate laterally displaced therefrom; (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate; (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere; (e) removing the compound semiconductor polycrystalline layer; (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor; and (g) then forming ohmic contacts on said devices.
Claim 32
Dependent Claim
18 words
The method of claim 24 wherein the heat treatment is conducted at a temperature of about 850° C.
Claim 33
Dependent Claim
21 words
The method of claim 21 wherein the buffer layer and extended region is heavily doped and of the same type conductivity.
Claim 34
Dependent Claim
17 words
The method of claim 28 wherein the dopant for the buffer layer and extended region is n+.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-27 | 1992-03-28 | 1992-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-27 | 1996-03-28 | 1996-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-27 | 2000-03-28 | 2000-09-27 | $7700.00 | Window Closed / Lapsed |