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US6133640A
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Three-dimensional structure memory
Assignee: ELM 3DS INNOVATONS LLC
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Filing: 1997-11-17
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Granted: 2000-10-17
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Expires: 2017-11-17
Abstract
Abstract A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
Inventors
- 👤 Glenn J. Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:57
CPC Classifications
H; H10; H10D; H10D84/00; B; B44; B44C; B44C1/00; B44C1/22; G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/846; G11C5/00; G11C5/02; G11C5/025; G11C5/04; H10B; H10B12/00; H10B12/50; H10B99/00; H10D88/00; H10W; H10W20/00; H10W20/20; H10W70/00; H10W70/60; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/80; G11C29/81; G11C29/848; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/30; H10W72/351; H10W72/352; H10W90/00; H10W90/20; H10W90/297; Y; Y10; Y10S; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
77 words
A stacked integrated circuit memory comprising: a first substantially rigid substrate having formed thereon one of a memory circuit and a memory controller circuit; at least one substantially flexible substrate having formed thereon the other of said memory circuit and said memory controller circuit and being bonded to the first substrate; and a bond bonding together the first substrate and the substantially flexible substrate, the bond having a withstand temperature compatible with comparatively high temperature semiconductor processes.
Claim 2
Dependent Claim
77 words
A stacked integrated circuit memory comprising: a first substantially rigid substrate having formed thereon one of a memory circuit and a memory controller circuit; at least one substantially flexible substrate having formed thereon the other of said memory circuit and said memory controller circuit and being bonded to the first substrate; and a bond bonding together the first substrate and the substantially flexible substrate, the bond having a withstand temperature compatible with comparatively high temperature semiconductor processes.
Claim 3
Dependent Claim
36 words
The apparatus of claim 1, wherein the first substrate has formed thereon the memory circuit and is part of a stack of memory circuit substrates, and the second substrate has formed thereon the memory controller circuit.
Claim 4
Dependent Claim
24 words
The apparatus of claim 2, wherein the first and second substrates are singulated die, the second substrate having greater area than the first substrate.
Claim 5
Dependent Claim
20 words
The apparatus of claim 3, wherein the second substrate has formed thereon additional circuitry separate from the memory controller circuit.
Claim 6
Dependent Claim
16 words
The apparatus of claim 4, wherein the additional circuitry is part of a graphics display subsystem.
Claim 7
Dependent Claim
12 words
The apparatus of claim 4, wherein the additional circuitry comprises a microprocessor.
Claim 8
Dependent Claim
14 words
The apparatus of claim 1, wherein the substantially flexible substrate includes memory I/O pads.
Claim 9
Dependent Claim
48 words
The apparatus of claim 7, wherein the memory circuit is formed proximate a top surface of the substantially flexible substrate, the top surface being bonded to the first substantially rigid substrate, and the memory I/O pads are formed proximate an opposite bottom surface of the substantially flexible substrate.
Claim 10
Dependent Claim
19 words
The apparatus of claim 1, wherein the memory circuit and the memory controller circuit are coupled by vertical interconnects.
Claim 11
Dependent Claim
22 words
The apparatus of claim 9, wherein said vertical interconnects include fine-grain vertical interconnects formed at a pitch of less than 100 μm.
Claim 12
Dependent Claim
19 words
The method of claim 10, wherein at least some of the fine-grain vertical interconnects are arrayed in two dimensions.
Claim 13
Dependent Claim
41 words
The apparatus of claim 10, wherein said memory circuit comprises a two-dimensional array of memory blocks, each memory block having formed proximate thereto an array of fine-grain vertical interconnects forming a first port coupling the memory block to the memory controller.
Claim 14
Dependent Claim
33 words
The apparatus of claim 12, wherein at least some memory blocks have formed proximate thereto an array of fine-grain vertical interconnects forming a second port coupling the memory block to the memory controller.
Claim 15
Dependent Claim
17 words
The apparatus of claim 1, wherein at least one of said memory circuits provides redundant memory locations.
Claim 16
Dependent Claim
20 words
The apparatus of claim 14, further comprising an additional substantially flexible substrate on which is formed a redundant memory circuit.
Claim 17
Dependent Claim
25 words
The apparatus of claim 15, wherein the memory controller circuit comprises ECC logic and is programmed to store ECC syndromes in the redundant memory circuit.
Claim 18
Dependent Claim
17 words
The apparatus of claim 14, wherein the memory controller circuit comprises logic for testing the memory circuit.
Claim 19
Dependent Claim
25 words
The apparatus of claim 17, wherein the memory controller circuit is programmed to substitute redundant memory locations for defective memory locations in the memory circuit.
Claim 20
Dependent Claim
51 words
The apparatus of claim 1, wherein the memory controller circuit comprises logic for performing at least one of the following functions: virtual memory management, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management, and database processing.
Claim 21
Dependent Claim
22 words
The apparatus of claim 1, further comprising a substrate having formed thereon a redundant memory controller, bonded to the substantially flexible substrate.
Claim 22
Dependent Claim
20 words
The apparatus of claim 1, further comprising a substrate having formed thereon a microprocessor, bonded to the substantially flexible substrate.
Claim 23
Dependent Claim
21 words
The apparatus of claim 1, wherein the memory controller circuit comprises sense amplifiers coupled to data lines of the memory circuit.
Claim 24
Dependent Claim
24 words
The apparatus of claim 22, wherein the sense amplifiers discriminate between more than two signal levels, each sense amplifier producing a multi-level output signal.
Claim 25
Dependent Claim
24 words
The apparatus of claim 22, wherein the sense amplifiers are sized so as to exhibit a switching speed of about 10 ns or less.
Claim 26
Dependent Claim
40 words
The apparatus of claim 1, wherein said memory controller circuit is fabricated using a semiconductor process technology, characterized by a particular deposition sequence, and said memory circuits are formed using a different process technology characterized by a different deposition sequence.
Claim 27
Dependent Claim
27 words
The apparatus of claim 25, wherein said different process technology is selected from a group consisting of: DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
Claim 28
Dependent Claim
49 words
The apparatus of claim 8 wherein said top surface and said first substantially rigid substrate include both interconnect metallization and non-interconnect metallization and are bonded together by thermal diffusion bonding, whereby thermal diffusion bonding simultaneously achieves electrical interconnection through said interconnect metallization and mechanical bonding through said non-interconnect metallization.
Claim 29
Dependent Claim
86 words
A stacked integrated circuit memory comprising: a first substantially rigid substrate having formed thereon one of a memory circuit and a memory controller circuit; at least one substantially flexible substrate having formed thereon the other of said memory circuit and said memory controller circuit and being bonded to the first substrate; and a compact two-dimensional array of fine-grain vertical interconnects interior to and extending between the first substrate and the substantially flexible substrate, interconnecting integrated circuitry formed on the first substrate and the substantially flexible substrate.
Claim 30
Dependent Claim
86 words
A stacked integrated circuit memory comprising: a first substantially rigid substrate having formed thereon one of a memory circuit and a memory controller circuit; at least one substantially flexible substrate having formed thereon the other of said memory circuit and said memory controller circuit and being bonded to the first substrate; and a compact two-dimensional array of fine-grain vertical interconnects interior to and extending between the first substrate and the substantially flexible substrate, interconnecting integrated circuitry formed on the first substrate and the substantially flexible substrate.
Claim 31
Dependent Claim
36 words
The apparatus of claim 28, wherein the first substrate has formed thereon the memory circuit and is part of a stack of memory circuit substrates, and the second substrate has formed thereon the memory controller circuit.
Claim 32
Dependent Claim
14 words
The apparatus of claim 28, wherein the substantially flexible substrate includes memory I/O pads.
Claim 33
Dependent Claim
19 words
The apparatus of claim 28, wherein the memory circuit and the memory controller circuit are coupled by vertical interconnects.
Claim 34
Dependent Claim
17 words
The apparatus of claim 28, wherein at least one of said memory circuits provides redundant memory locations.
Claim 35
Dependent Claim
51 words
The apparatus of claim 28, wherein the memory controller circuit comprises logic for performing at least one of the following functions: virtual memory management, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management, and database processing.
Claim 36
Dependent Claim
23 words
The apparatus of claim 28, further comprising a second substrate having formed thereon a redundant memory controller, bonded to the substantially flexible substrate.
Claim 37
Dependent Claim
21 words
The apparatus of claim 28, further comprising a second substrate having formed thereon a microprocessor, bonded to the substantially flexible substrate.
Claim 38
Dependent Claim
21 words
The apparatus of claim 28, wherein the memory controller circuit comprises sense amplifiers coupled to data lines of the memory circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-17 | 2004-04-17 | 2004-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-17 | 2008-04-17 | 2008-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-17 | 2012-04-17 | 2012-10-17 | $7700.00 | Window Closed / Lapsed |