Patent US6118167A successfully refreshed from Google Patents.
US6118167A
Expired / Lapsed
US
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Polysilicon coated nitride-lined shallow trench
Assignee: National Semiconductor Corp
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Filing: 1997-11-13
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Granted: 2000-09-12
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Expires: 2017-11-13
Abstract
Abstract A polycrystalline silicon coated nitride-lined shallow trench technique for isolating active regions on an integrated circuit involves reducing the oxide encroachment and the "bird's beak" structure. The technique involves forming an isolation trench, or recess, in the substrate. This recess is then lined with a layer of silicon dioxide layer, and then a layer of silicon nitride. Subsequently, a polycrystalline silicon material is deposited in the recess and is then oxidized to form a field oxide and planarized. Since the recess is nitride-lined, which prevents oxidizing species from reaching the oxide layer beneath the nitride layer, and the polycrystalline silicon is oxidized, the result is zero oxide encroachment resulting in the elimination of the "bird's beak" structure.
Inventors
- 👤 Eugene DiSimone
- 👤 Paramjit Singh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:01
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/014; H10W10/10; H10W10/13; H10W10/17
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
87 words
An apparatus including an integrated circuit having an isolated region, the integrated circuit comprising: a substrate of semiconductor material having a first cavity disposed therein, said first cavity having sidewalls and a bottom; a dielectric layer formed in the first cavity; an oxide-resistant layer formed on the dielectric layer, wherein the dielectric layer and the oxide-resistant layer together form a second cavity lining the sidewalls and the bottom of the first cavity; and an oxidized polycrystalline silicon layer formed in the second cavity and within the substrate.
Claim 2
Independent Claim
87 words
An apparatus including an integrated circuit having an isolated region, the integrated circuit comprising: a substrate of semiconductor material having a first cavity disposed therein, said first cavity having sidewalls and a bottom; a dielectric layer formed in the first cavity; an oxide-resistant layer formed on the dielectric layer, wherein the dielectric layer and the oxide-resistant layer together form a second cavity lining the sidewalls and the bottom of the first cavity; and an oxidized polycrystalline silicon layer formed in the second cavity and within the substrate.
Claim 3
Dependent Claim
12 words
The apparatus of claim 1, wherein the oxide-resistant layer comprises silicon nitride.
Claim 4
Dependent Claim
19 words
The apparatus of claim 1, wherein the oxidized polycrystalline silicon layer fills at least two-thirds of the second cavity.
Claim 5
Dependent Claim
19 words
The apparatus of claim 1, wherein the oxide-resistant layer formed on the first dielectric layer is approximately 400 angstroms.
Claim 6
Dependent Claim
16 words
The apparatus of claim 1, wherein the first cavity has a depth of approximately one micron.
Claim 7
Dependent Claim
17 words
The apparatus of claim 1, wherein the oxidized polycrystalline silicon layer is substantially contained within the substrate.
Claim 8
Dependent Claim
16 words
The apparatus of claim 1, wherein the oxidized polycrystalline silicon layer fills the entire second cavity.
Claim 9
Dependent Claim
33 words
The apparatus of claim 1, wherein an upper surface of the first cavity, an upper surface of the second cavity and an upper surface of the oxidized polycrystalline silicon layer are substantially coplanar.
Claim 10
Independent Claim
89 words
An apparatus including an integrated circuit having an isolated region, the integrated circuit comprising: a substrate of semiconductor material having a first cavity disposed therein, said first cavity having sidewalls and a bottom; a dielectric layer formed in the first cavity; an oxide-resistant layer formed on the dielectric layer, wherein the dielectric layer and the oxide-resistant layer together form a second cavity lining the sidewalls and the bottom of the first cavity; and an oxidized polycrystalline silicon layer formed in the second cavity and substantially filling the second cavity.
Claim 11
Independent Claim
89 words
An apparatus including an integrated circuit having an isolated region, the integrated circuit comprising: a substrate of semiconductor material having a first cavity disposed therein, said first cavity having sidewalls and a bottom; a dielectric layer formed in the first cavity; an oxide-resistant layer formed on the dielectric layer, wherein the dielectric layer and the oxide-resistant layer together form a second cavity lining the sidewalls and the bottom of the first cavity; and an oxidized polycrystalline silicon layer formed in the second cavity and substantially filling the second cavity.
Claim 12
Dependent Claim
12 words
The apparatus of claim 9, wherein the oxide-resistant layer comprises silicon nitride.
Claim 13
Dependent Claim
19 words
The apparatus of claim 9, wherein the oxidized polycrystalline silicon layer fills at least two-thirds of the second cavity.
Claim 14
Dependent Claim
19 words
The apparatus of claim 9, wherein the oxide-resistant layer formed on the first dielectric layer is approximately 400 angstroms.
Claim 15
Dependent Claim
16 words
The apparatus of claim 9, wherein the first cavity has a depth of approximately one micron.
Claim 16
Dependent Claim
17 words
The apparatus of claim 9, wherein the oxidized polycrystalline silicon layer is substantially contained within the substrate.
Claim 17
Dependent Claim
33 words
The apparatus of claim 9, wherein an upper surface of the first cavity, an upper surface of the second cavity and an upper surface of the oxidized polycrystalline silicon layer are substantially coplanar.
Claim 18
Independent Claim
92 words
An apparatus including an integrated circuit having an isolated region, the integrated circuit comprising: a substrate of semiconductor material having a first cavity disposed therein, said first cavity having sidewalls and a bottom; a dielectric layer lining the sidewalls and the bottom of the first cavity; an oxide-resistant layer lining the dielectric layer, wherein the dielectric layer and oxide-resistant layer together form a second cavity lining the sidewalls and the bottom of the first cavity; and an oxidized polycrystalline silicon layer formed in the second cavity and substantially filling the second cavity.
Claim 19
Independent Claim
92 words
An apparatus including an integrated circuit having an isolated region, the integrated circuit comprising: a substrate of semiconductor material having a first cavity disposed therein, said first cavity having sidewalls and a bottom; a dielectric layer lining the sidewalls and the bottom of the first cavity; an oxide-resistant layer lining the dielectric layer, wherein the dielectric layer and oxide-resistant layer together form a second cavity lining the sidewalls and the bottom of the first cavity; and an oxidized polycrystalline silicon layer formed in the second cavity and substantially filling the second cavity.
Claim 20
Dependent Claim
16 words
The apparatus of claim 16, wherein the first cavity has a depth of approximately one micron.
Claim 21
Dependent Claim
17 words
The apparatus of claim 16, wherein the oxidized polycrystalline silicon layer is substantially contained within the substrate.
Claim 22
Dependent Claim
16 words
The apparatus of claim 16, wherein the oxidized polycrystalline silicon layer fills the entire second cavity.
Claim 23
Dependent Claim
33 words
The apparatus of claim 16, wherein an upper surface of the first cavity, an upper surface of the second cavity and an upper surface of the oxidized polycrystalline silicon layer are substantially coplanar.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-12 | 2004-03-13 | 2004-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-12 | 2008-03-13 | 2008-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-12 | 2012-03-13 | 2012-09-12 | $7700.00 | Window Closed / Lapsed |