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US5410176A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit with planarized shallow trench isolation

Assignee: STMicroelectronics lnc USA
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Filing: 1993-05-24
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Granted: 1995-04-25
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Expires: 2013-05-24
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Abstract

Abstract A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.

Inventors

  • 👤 Fu-Tai Liou
  • 👤 Fusen E. Chen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 21:21
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0142; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 111 words
An integrated circuit formed at a semiconducting surface of a body, comprising: a plurality of active regions at said surface; and a first isolation structure formed into a recess at said surface between a pair of said plurality of active regions, comprising: sidewall spacers along the sides of said recess consisting essentially of deposited silicon dioxide; and thermal silicon dioxide filling substantially the remainder of said recess between said sidewall spacers, said thermal silicon dioxide having a top surface substantially coplanar with surfaces of said first and second ones of said plurality of active regions and having a bottom surface that is substantially coplanar with bottom surfaces of said sidewall spacers.
Claim 2
Dependent Claim 111 words
An integrated circuit formed at a semiconducting surface of a body, comprising: a plurality of active regions at said surface; and a first isolation structure formed into a recess at said surface between a pair of said plurality of active regions, comprising: sidewall spacers along the sides of said recess consisting essentially of deposited silicon dioxide; and thermal silicon dioxide filling substantially the remainder of said recess between said sidewall spacers, said thermal silicon dioxide having a top surface substantially coplanar with surfaces of said first and second ones of said plurality of active regions and having a bottom surface that is substantially coplanar with bottom surfaces of said sidewall spacers.
Claim 3
Dependent Claim 21 words
The integrated circuit of claim 1, wherein said thermal silicon dioxide is formed by the thermal oxidation of epitaxially grown silicon.
Claim 4
Dependent Claim 37 words
The integrated circuit of claim 1, further comprising: a second isolation structure formed into a recess at said surface between a pair of said plurality of active regions, said second isolation structure comprising a deposited insulating layer.
Claim 5
Dependent Claim 14 words
The integrated circuit of claim 3, wherein said deposited insulating layer comprises silicon dioxide.
Claim 6
Dependent Claim 18 words
The integrated circuit of claim 1, further comprising: active devices formed near said surfaces of said active regions.
Claim 7
Dependent Claim 15 words
The integrated circuit of claim 1, further comprising: a conductor overlying said first isolation structure.
Claim 8
Dependent Claim 124 words
An integrated circuit structure formed by a method comprising the steps of: forming a masking layer over selected locations of a semiconducting surface corresponding to active regions, said masking layer comprising an oxidation barrier material; etching a recess into said surface at a location not covered by said masking layer; forming sidewall spacers consisting essentially of silicon dioxide along the sides of said recess, in such a manner that semiconducting material is exposed at the bottom of said recess; selectively depositing silicon at the exposed bottom of said recess, in such a manner that said silicon is not deposited along said sidewall spacers; and oxidizing said deposited silicon; wherein said oxidizing step also oxidizes corner locations of said active regions adjacent to said recess.
Claim 9
Dependent Claim 124 words
An integrated circuit structure formed by a method comprising the steps of: forming a masking layer over selected locations of a semiconducting surface corresponding to active regions, said masking layer comprising an oxidation barrier material; etching a recess into said surface at a location not covered by said masking layer; forming sidewall spacers consisting essentially of silicon dioxide along the sides of said recess, in such a manner that semiconducting material is exposed at the bottom of said recess; selectively depositing silicon at the exposed bottom of said recess, in such a manner that said silicon is not deposited along said sidewall spacers; and oxidizing said deposited silicon; wherein said oxidizing step also oxidizes corner locations of said active regions adjacent to said recess.
Claim 10
Dependent Claim 12 words
The structure of claim 7, wherein said masking layer comprises silicon nitride.
Claim 11
Dependent Claim 34 words
The structure of claim 7, wherein said step of forming sidewall spacers comprises: depositing a conformal layer of silicon dioxide overall; and anisotropically etching said layer of silicon dioxide to form said sidewall spacers.
Claim 12
Dependent Claim 18 words
The structure of claim 7, wherein said step of selective depositing silicon comprises selective epitaxial growth of silicon.
Claim 13
Dependent Claim 24 words
The structure of claim 10, wherein the thickness of said deposited silicon in said recess is approximately half of the depth of said recess.
Claim 14
Dependent Claim 24 words
The structure of claim 7, wherein the thickness of said deposited silicon in said recess is approximately half of the depth of said recess.
Claim 15
Dependent Claim 15 words
The structure of claim 7, wherein said step of etching a recess is substantially anisotropic.
Claim 16
Dependent Claim 34 words
The structure of claim 7, wherein said step of etching a recess etches first and second recesses at first and second locations of said surface, said first recess being wider than said second recess.
Claim 17
Dependent Claim 62 words
The structure of claim 7, wherein said step of forming sidewall spacers comprises: depositing a conformal layer of silicon dioxide overall; and anisotropically etching said layer of silicon dioxide to form said sidewall spacers in said first recess; and wherein the thickness of said layer of silicon dioxide is such that said second recess remains filled therewith after said anisotropically etching step.
Claim 18
Dependent Claim 38 words
The structure of claim 7, wherein said step of depositing silicon comprises selective epitaxial growth of silicon; and wherein the thickness of said deposited silicon in said recess is approximately half of the depth of said first recess.

References Cited (Backward Citations)

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US4661202A Cited
EP0155698A2 Cited
US4740480A Cited
US4842675A Cited
JPS63258040A Cited
US4958213A Cited
US5073813A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-04-24 1998-10-24 1999-04-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-04-24 2002-10-24 2003-04-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-04-24 2006-10-24 2007-04-25 $7700.00 Window Closed / Lapsed

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