US6080672A
Expired / Lapsed
US
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Self-aligned contact formation for semiconductor devices
Assignee: Micron Technology Inc
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Filing: 1997-08-20
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Granted: 2000-06-27
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Expires: 2017-08-20
Abstract
Abstract In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.
Inventors
- 👤 Werner Juengling
- 👤 Kirk Prall
- 👤 Trung T. Doan
- 👤 Guy T. Blalock
- 👤 David Dickerson
- 👤 David S. Becker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:50
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10B; H10B12/00; H10B12/01; H10B12/09; H10D84/0123; H10D84/0126; H10D84/0149; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
46 words
A method of forming an integrated circuit, comprising the steps of: forming a gate stack on the integrated circuit; forming an insulating film on the integrated circuit; planarizing the insulating film; forming a gate contact opening through at least a portion of the planarized insulating film.
Claim 2
Independent Claim
46 words
A method of forming an integrated circuit, comprising the steps of: forming a gate stack on the integrated circuit; forming an insulating film on the integrated circuit; planarizing the insulating film; forming a gate contact opening through at least a portion of the planarized insulating film.
Claim 3
Dependent Claim
36 words
The method of claim 1, wherein the gate contact opening is formed by removing the insulator, spacer and insulating film by etching; and wherein the insulator, spacer and insulating film are etched at substantially similar rates.
Claim 4
Dependent Claim
15 words
The method of claim 1, wherein the integrated circuit is a dynamic random access memory.
Claim 5
Dependent Claim
43 words
The method of claim 1, wherein the insulating film comprises tetraethyloxysilicate (TEOS) and borophosphosilicate glass (BPSG); wherein the thickness of the TEOS is between 100 angstroms and 500 angstroms; and wherein the thickness of the BPSG is between 1000 angstroms and 3000 angstroms.
Claim 6
Dependent Claim
28 words
The method of claim 1, wherein the gate stack comprises: gate dielectric on a base layer; a conductor on the gate dielectric; and an insulator on the conductor.
Claim 7
Dependent Claim
12 words
The method of claim 1, wherein the gate stack is a wordline.
Claim 8
Dependent Claim
28 words
The method of claim 1, wherein the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit.
Claim 9
Independent Claim
121 words
A method of forming a dynamic random access memory (DRAM), comprising the steps of: forming a gate dielectric on a base layer of the DRAM; forming a conductor on the gate dielectric; forming an insulator on the conductor; removing selected areas of gate dielectric, conductor and insulator to form a gate stack on the DRAM; forming a spacer on a sidewall of the gate stack; forming an insulating film on the DRAM; planarizing the insulating film; forming a gate contact opening on the DRAM after the gate stack is formed; wherein the gate contact opening is formed by removing the insulator, spacer and insulating film by etching; and wherein the insulator, spacer and insulating film are etched at substantially similar rates.
Claim 10
Independent Claim
121 words
A method of forming a dynamic random access memory (DRAM), comprising the steps of: forming a gate dielectric on a base layer of the DRAM; forming a conductor on the gate dielectric; forming an insulator on the conductor; removing selected areas of gate dielectric, conductor and insulator to form a gate stack on the DRAM; forming a spacer on a sidewall of the gate stack; forming an insulating film on the DRAM; planarizing the insulating film; forming a gate contact opening on the DRAM after the gate stack is formed; wherein the gate contact opening is formed by removing the insulator, spacer and insulating film by etching; and wherein the insulator, spacer and insulating film are etched at substantially similar rates.
Claim 11
Dependent Claim
43 words
The method of claim 8, wherein the insulating film comprises tetraethyloxysilicate (TEOS) and borophosphosilicate glass (BPSG); wherein the thickness of the TEOS is between 100 angstroms and 500 angstroms; and wherein the thickness of the BPSG is between 1000 angstroms and 3000 angstroms.
Claim 12
Dependent Claim
10 words
The method of claim 8, wherein the spacer comprises nitride.
Claim 13
Dependent Claim
12 words
The method of claim 8, wherein the gate stack is a wordline.
Claim 14
Dependent Claim
27 words
The method of claim 8, wherein the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the DRAM.
Claim 15
Independent Claim
55 words
A method of forming contacts in a dynamic random access memory (DRAM), comprising the steps of: forming a spacer on a sidewall of a gate stack of the DRAM; forming dielectric on the DRAM; forming gate and bitline contact openings through the dielectric; and forming gate and bitline contacts in self-alignment to the gate stack.
Claim 16
Independent Claim
55 words
A method of forming contacts in a dynamic random access memory (DRAM), comprising the steps of: forming a spacer on a sidewall of a gate stack of the DRAM; forming dielectric on the DRAM; forming gate and bitline contact openings through the dielectric; and forming gate and bitline contacts in self-alignment to the gate stack.
Claim 17
Dependent Claim
32 words
The method of claim 13, wherein the step of forming the gate and bitline contacts is performed with an etch that removes the additional dielectric, but does not substantially remove the spacer.
Claim 18
Independent Claim
197 words
A method of forming a dynamic random access memory (DRAM), comprising the steps of: forming groups n and p wells on a base layer wherein such groups are separated by field oxide; forming a gate oxide on the base layer; forming a conductor on the gate dielectric; forming silicon nitride on the conductor; forming gate stacks on the DRAM; forming nitride spacers on the sidewalls of the gate stacks; forming borophosphosilicate glass (BPSG) on the DRAM; planarizing the BPSG with chemical mechanical planarization to form a substantially flat topography on the surface of the DRAM; forming a gate contact opening on the DRAM after the gate stacks are formed; forming additional dielectric on the DRAM; forming gate and bitline contact openings through the additional dielectric; forming gate and bitline contacts in self-alignment to the gate stacks; wherein the gate contact opening is formed by removing the insulator, spacer and insulating film by etching; wherein the silicon nitride, nitride spacer and BPSG are etched at substantially similar rates; and wherein the step of forming the gate and bitline contact openings is performed with an etch that removes the additional dielectric, but does not substantially remove the nitride spacer.
Claim 19
Independent Claim
197 words
A method of forming a dynamic random access memory (DRAM), comprising the steps of: forming groups n and p wells on a base layer wherein such groups are separated by field oxide; forming a gate oxide on the base layer; forming a conductor on the gate dielectric; forming silicon nitride on the conductor; forming gate stacks on the DRAM; forming nitride spacers on the sidewalls of the gate stacks; forming borophosphosilicate glass (BPSG) on the DRAM; planarizing the BPSG with chemical mechanical planarization to form a substantially flat topography on the surface of the DRAM; forming a gate contact opening on the DRAM after the gate stacks are formed; forming additional dielectric on the DRAM; forming gate and bitline contact openings through the additional dielectric; forming gate and bitline contacts in self-alignment to the gate stacks; wherein the gate contact opening is formed by removing the insulator, spacer and insulating film by etching; wherein the silicon nitride, nitride spacer and BPSG are etched at substantially similar rates; and wherein the step of forming the gate and bitline contact openings is performed with an etch that removes the additional dielectric, but does not substantially remove the nitride spacer.
Claim 20
Dependent Claim
50 words
The method of claim 15, further comprising the step of forming tetraethyloxysilicate (TEOS) on the DRAM before BPSG is formed on the DRAM; wherein the thickness of the TEOS is between 100 angstroms and 500 angstroms; and wherein the thickness of the BPSG is between 1000 angstroms and 3000 angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-27 | 2003-12-27 | 2004-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-27 | 2007-12-27 | 2008-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-27 | 2011-12-27 | 2012-06-27 | $7700.00 | Window Closed / Lapsed |