US5863837A
Expired / Lapsed
US
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Method of manufacturing semiconductor device
Assignee: Toshiba Corp
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Filing: 1997-03-21
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Granted: 1999-01-26
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Expires: 2017-03-21
Abstract
Abstract This invention is related to a method of manufacturing a semiconductor including a MOSFET. The method comprises a step of forming an opening in a first insulating layer covering a second insulating layer and a surface of semiconductor substrate, so that the second insulating layer covering a gate electrode, and a surface of a source region and a drain region are exposed, a step of burying a conductive material in the opening, and a step of etching the conductive material so that a surface of the second insulating layer is exposed.
Inventors
- 👤 Akira Sudo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:12
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
76 words
A method of manufacturing a semiconductor device, comprising the steps of: forming an opening in a first insulating layer covering a second insulating layer and a surface of semiconductor substrate, so that the second insulating layer covering a gate electrode, and a surface of a source region and a drain region are exposed; burying a conductive material in the opening; and etching the conductive material so that a surface of the second insulating layer is exposed.
Claim 2
Independent Claim
76 words
A method of manufacturing a semiconductor device, comprising the steps of: forming an opening in a first insulating layer covering a second insulating layer and a surface of semiconductor substrate, so that the second insulating layer covering a gate electrode, and a surface of a source region and a drain region are exposed; burying a conductive material in the opening; and etching the conductive material so that a surface of the second insulating layer is exposed.
Claim 3
Dependent Claim
31 words
The method of manufacturing a semiconductor device according to claim 1, wherein a speed of etching the first insulating layer is faster than a speed of etching the second insulating layer.
Claim 4
Dependent Claim
33 words
The method of manufacturing a semiconductor device according to claim 1, wherein the opening is made by an anisotropic etching method using an etching mask having a first opening over the gate electrode.
Claim 5
Dependent Claim
28 words
The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating layer is a silicon dioxide (SiO 2 ) layer made from TEOS (tetraethoxysilane).
Claim 6
Dependent Claim
21 words
The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating layer is made from silicon nitride.
Claim 7
Dependent Claim
23 words
The method of manufacturing a semiconductor device according to claim 1, wherein the etching step is accomplished by a CMP (chemical mechanical polishing).
Claim 8
Independent Claim
158 words
A method of manufacturing a semiconductor device, comprising the steps of: depositing a material of gate electrode on a gate insulating film; depositing a first insulating layer on the material of gate electrode; forming a gate electrode by etching the material of gate electrode and the first insulating layer; forming a second insulating layer along a side surface of the gate electrode; forming a source region and drain region in a surface of the semiconductor substrate; depositing a third insulating layer over the gate electrode and the semiconductor substrate; forming an opening in the third insulating layer so that the first and second insulating layer and a part of a surface of the source region and a part of a surface of the drain region are exposed; burying a conductive material in the opening; and dividing the conductive material into two portions by etching the conductive material so that a surface of the second insulating layer is exposed.
Claim 9
Independent Claim
158 words
A method of manufacturing a semiconductor device, comprising the steps of: depositing a material of gate electrode on a gate insulating film; depositing a first insulating layer on the material of gate electrode; forming a gate electrode by etching the material of gate electrode and the first insulating layer; forming a second insulating layer along a side surface of the gate electrode; forming a source region and drain region in a surface of the semiconductor substrate; depositing a third insulating layer over the gate electrode and the semiconductor substrate; forming an opening in the third insulating layer so that the first and second insulating layer and a part of a surface of the source region and a part of a surface of the drain region are exposed; burying a conductive material in the opening; and dividing the conductive material into two portions by etching the conductive material so that a surface of the second insulating layer is exposed.
Claim 10
Dependent Claim
36 words
The method of manufacturing a semiconductor device according to claim 7, wherein a speed of etching the first insulating layer and the second insulating layer is faster than a speed of etching the third insulating layer.
Claim 11
Dependent Claim
34 words
The method of manufacturing a semiconductor device according to claim 7, wherein a total thickness of the gate electrode and the first insulating layer is equal to a thickness of the third insulating layer.
Claim 12
Dependent Claim
23 words
The method of manufacturing a semiconductor device according to claim 7, wherein the dividing step is accomplished by a CMP (chemical mechanical polishing).
Claim 13
Dependent Claim
41 words
The method of manufacturing a semiconductor device according to claim 7, further comprising the step of; forming a conductive film on the part of the surface of the source region and on the part of the surface of the drain region.
Claim 14
Dependent Claim
34 words
The method of manufacturing a semiconductor device according to claim 11, wherein the conductive material is made of a metal having a high melting point, and the conductive layer is made of a silicide.
Claim 15
Dependent Claim
30 words
The method of manufacturing a semiconductor device according to claim 11, wherein the conductive material is made of an aluminum, and the conductive layer is made of a barrier metal.
References Cited (Backward Citations)
US4822754A
Cited
US5231051A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-25 | 2002-07-27 | 2003-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-25 | 2006-07-27 | 2007-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-25 | 2010-07-27 | 2011-01-26 | $7700.00 | Window Closed / Lapsed |