US5488011A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming contact areas between vertical conductors
Assignee: Micron Technology Inc
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Filing: 1994-11-08
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Granted: 1996-01-30
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Expires: 2014-11-08
Abstract
Abstract A method of forming a contact area between two vertical structures. A first layer of material conforming to an extending between vertical sidewalls is covered with a mask layer. The mask layer is patterned and etched to remove the horizontal region of the mask layer between the vertical sidewalls, thereby exposing the first layer of material at the desired location of the contact area, while retaining at least a portion of the vertical regions of the mask layer. Using the remaining vertical regions of the mask layer as etch mask, the exposed portions of the first layer are then etched away to form the contact area. Another aspect of the invention provides a method of making a DRAM that utilizes a capacitor insulating layer over the capacitor second conductor (or cell poly) to self-align the bit line contact to the capacitor second conductor. In accordance with this aspect of the invention, a capacitor is formed over a semiconductor wafer. The capacitor includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. A capacitor insulating layer is formed on the second conductor. The capacitor insulating layer is patterned and etched to expose portions of the second conductor at the desired location of the bit line contact. Then, using the capacitor insulating layer as a hard mask, the exposed portions of the second conductor are etched away in the area in which the bit line contact will subsequently be formed.
Inventors
- 👤 Thomas A. Figura
- 👤 Kirk D. Prall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:21
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10P; H10P14/00; H10P14/40
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
125 words
A method of making an integrated circuit device, comprising: a. forming first and second structures each having a vertical sidewall; b. forming a first layer of material conforming to, and extending between the vertical sidewalls; c. forming a mask layer conforming to the first layer, wherein the mask layer has a horizontal region between the vertical sidewalls and vertical regions along the vertical sidewalls; d. patterning and etching the mask layer to remove the horizontal region of the mask layer, thereby exposing portions of the first layer between the vertical sidewalls, while retaining at least a portion of each vertical region of the mask layer; and e. using the remaining mask layer as an etch mask, etching away the exposed portions of the first layer.
Claim 2
Independent Claim
125 words
A method of making an integrated circuit device, comprising: a. forming first and second structures each having a vertical sidewall; b. forming a first layer of material conforming to, and extending between the vertical sidewalls; c. forming a mask layer conforming to the first layer, wherein the mask layer has a horizontal region between the vertical sidewalls and vertical regions along the vertical sidewalls; d. patterning and etching the mask layer to remove the horizontal region of the mask layer, thereby exposing portions of the first layer between the vertical sidewalls, while retaining at least a portion of each vertical region of the mask layer; and e. using the remaining mask layer as an etch mask, etching away the exposed portions of the first layer.
Claim 3
Dependent Claim
25 words
A method of making an integrated circuit device according to claim 1 wherein the first layer is preferentially etchable with respect to the mask layer.
Claim 4
Dependent Claim
32 words
A method of making an integrated circuit device according to claim 1, wherein the first layer is made of electrically conductive material and the mask layer is made of electrically insulating material.
Claim 5
Independent Claim
104 words
A method of making an integrated circuit device, comprising: a. forming a capacitor over a semiconductor wafer, the capacitor comprising a vertical first conductor, a dielectric layer on the first conductor and a second conductor in the dieletrically layer, whereby the second conductor has a vertical portion parallel to the first conductor; b. forming a capacitor insulating layer on the second conductor; c. patterning and etching the capacitor insulating layer to expose portions of the second conductor at a location of a bit line contact; and d. using the capacitor insulating layer as mask, etching away the exposed portions of the second conducting layer.
Claim 6
Independent Claim
104 words
A method of making an integrated circuit device, comprising: a. forming a capacitor over a semiconductor wafer, the capacitor comprising a vertical first conductor, a dielectric layer on the first conductor and a second conductor in the dieletrically layer, whereby the second conductor has a vertical portion parallel to the first conductor; b. forming a capacitor insulating layer on the second conductor; c. patterning and etching the capacitor insulating layer to expose portions of the second conductor at a location of a bit line contact; and d. using the capacitor insulating layer as mask, etching away the exposed portions of the second conducting layer.
Claim 7
Dependent Claim
28 words
A method of making an integrated circuit device according to claim 4, wherein the capacitor insulating layer is etched back to the vertical portion of the second conductor.
Claim 8
Dependent Claim
22 words
A method of making an integrated circuit device according to claim 4, wherein the capacitor insulating layer is made of silicon dioxide.
Claim 9
Dependent Claim
22 words
A method of making an integrated circuit device according to claim 4, wherein the capacitor insulating layer is made of silicon nitride.
Claim 10
Dependent Claim
23 words
A method of making an integrated circuit device according to claim 4, wherein the capacitor insulating layer is etched using an isotropic etch.
Claim 11
Independent Claim
186 words
A method of making an integrated circuit device, comprising: a. forming on a semiconductor wafer a plurality of transistors each comprising a gate insulating layer on a substrate and a gate electrode on the gate insulating layer; b. forming first and second source/drain regions on the substrate adjacent to sides of at least one of the gate electrodes; c. forming a lower insulating layer over the substrate; d. patterning and etching the lower insulating layer to define a capacitor container in the lower insulating layer and to expose portions of the first source/drain region within the capacitor container; e. forming a vertical first conductor in the capacitor container so that a portion of the first conductor contacts the first source/drain region; f. forming a dielectric layer on the first conductor; g. forming a second conductor on the dielectric layer, whereby the second conductor has a vertical portion parallel to the first conductor; h. forming a capacitor insulating layer on the second conductor; and i. patterning and etching the capacitor insulating layer to expose portions of the second conductor at a location of a bit line contact.
Claim 12
Independent Claim
186 words
A method of making an integrated circuit device, comprising: a. forming on a semiconductor wafer a plurality of transistors each comprising a gate insulating layer on a substrate and a gate electrode on the gate insulating layer; b. forming first and second source/drain regions on the substrate adjacent to sides of at least one of the gate electrodes; c. forming a lower insulating layer over the substrate; d. patterning and etching the lower insulating layer to define a capacitor container in the lower insulating layer and to expose portions of the first source/drain region within the capacitor container; e. forming a vertical first conductor in the capacitor container so that a portion of the first conductor contacts the first source/drain region; f. forming a dielectric layer on the first conductor; g. forming a second conductor on the dielectric layer, whereby the second conductor has a vertical portion parallel to the first conductor; h. forming a capacitor insulating layer on the second conductor; and i. patterning and etching the capacitor insulating layer to expose portions of the second conductor at a location of a bit line contact.
Claim 13
Dependent Claim
28 words
A method of making an integrated circuit device according to claim 9, wherein the capacitor insulating layer is etched back to the vertical portion of the second conductor.
Claim 14
Dependent Claim
31 words
A method of making an integrated circuit device according to claim 9, further comprising, using the capacitor insulating layer as a mask, etching away the exposed portions of the second conductor.
Claim 15
Dependent Claim
80 words
A method of making an integrated circuit device according to claim 9, further comprising: a. forming an upper insulating layer over the capacitor insulating layer; b. patterning and etching the upper insulating layer and continuing to etch down to expose portions of the second source/drain region; and c. forming a bit line contact contacting the exposed portions of the second source/drain region, wherein the bit line contact is aligned with and parallel to the vertical portion of the second conductor.
Claim 16
Independent Claim
195 words
A method of making an integrated circuit device, comprising: a. forming on a semiconductor wafer a plurality of transistors each comprising a gate insulating layer and a gate electrode on the gate insulating layer; b. forming a plurality of source/drain regions on the substrate adjacent to sides of at least one of the gate electrodes; c. forming a lower insulating layer over the substrate; d. patterning and etching the lower insulating layer to define a bit line contact corridor above one of the source/drain regions and to expose the source/drain region within the bit line contact corridor; e. depositing electrically conductive material in the bit line contact corridor to form a bit line contact corridor plug contacting the exposed source/drain region; f. forming a vertical first conductor over the lower insulating layer; g. forming a dielectric layer on the first conductor; h. forming a second conductor on the dielectric layer, whereby the second conductor has a vertical portion parallel to the first conductor; i. forming a capacitor insulating layer on the second conductor; and j. patterning and etching the capacitor insulating layer to expose portions of the second conductor over the bit line contact corridor.
Claim 17
Independent Claim
195 words
A method of making an integrated circuit device, comprising: a. forming on a semiconductor wafer a plurality of transistors each comprising a gate insulating layer and a gate electrode on the gate insulating layer; b. forming a plurality of source/drain regions on the substrate adjacent to sides of at least one of the gate electrodes; c. forming a lower insulating layer over the substrate; d. patterning and etching the lower insulating layer to define a bit line contact corridor above one of the source/drain regions and to expose the source/drain region within the bit line contact corridor; e. depositing electrically conductive material in the bit line contact corridor to form a bit line contact corridor plug contacting the exposed source/drain region; f. forming a vertical first conductor over the lower insulating layer; g. forming a dielectric layer on the first conductor; h. forming a second conductor on the dielectric layer, whereby the second conductor has a vertical portion parallel to the first conductor; i. forming a capacitor insulating layer on the second conductor; and j. patterning and etching the capacitor insulating layer to expose portions of the second conductor over the bit line contact corridor.
Claim 18
Dependent Claim
28 words
A method of making an integrated circuit device according to claim 13, wherein the capacitor insulating layer is etched back to the vertical portion of the second conductor.
Claim 19
Dependent Claim
31 words
A method of making an integrated circuit device according to claim 13, further comprising, using the capacitor insulating layer as a mask, etching away the exposed portions of the second conductor.
Claim 20
Dependent Claim
83 words
A method of making an integrated circuit device according to claim 13, further comprising: a. forming an upper insulating layer over the capacitor insulating layer; b. patterning and etching the upper insulating layer and continuing to etch down to expose portions of the bit line contact corridor plug; and c. forming a bit line contact contacting the exposed portions of the bit line corridor plug, wherein the bit line contact is aligned with and parallel to the vertical portion of the second conductor.
Claim 21
Independent Claim
115 words
A method of making an integrated circuit device, comprising: a. forming a plurality of capacitors over a semiconductor wafer, each capacitor comprising a vertical first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer, wherein the second conductor has a vertical portion parallel to the first conductor and a horizontal portion bridging between adjacent capacitors; b. forming a capacitor insulating layer on the second conductor; c. patterning and etching the capacitor insulating layer to expose portions of the second conductor at a location of the bit line contact; and d. using the capacitor insulating layer as a mask, etching away the exposed portions of the second conducting layer.
Claim 22
Independent Claim
115 words
A method of making an integrated circuit device, comprising: a. forming a plurality of capacitors over a semiconductor wafer, each capacitor comprising a vertical first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer, wherein the second conductor has a vertical portion parallel to the first conductor and a horizontal portion bridging between adjacent capacitors; b. forming a capacitor insulating layer on the second conductor; c. patterning and etching the capacitor insulating layer to expose portions of the second conductor at a location of the bit line contact; and d. using the capacitor insulating layer as a mask, etching away the exposed portions of the second conducting layer.
Claim 23
Dependent Claim
28 words
A method of making an integrated circuit device according to claim 17, wherein the capacitor insulating layer is etched back to the vertical portion of the second conductor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |